Xiang Wang uploaded patch set #2 to this change.

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arch/riscv: Fix exception handling when CONFIG_RISCV_WORKING_HARTID not equal 0

Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
---
M src/arch/riscv/trap_util.S
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/37461/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic45560b4bfbf9366425ef4006ac2765113457349
Gerrit-Change-Number: 37461
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <merle@hardenedlinux.org>
Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-Reviewer: Philipp Hug <philipp@hug.cx>
Gerrit-Reviewer: Xiang Wang <merle@hardenedlinux.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich@gmail.com>
Gerrit-CC: Shawn C <citypw@hardenedlinux.org>
Gerrit-MessageType: newpatchset