234 comments:
File src/mainboard/asus/p2b-f/irq_tables.c:
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
line over 96 characters
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
space required after that close brace '}'
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
line over 96 characters
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
space required after that close brace '}'
Patch Set #1, Line 39: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
line over 96 characters
Patch Set #1, Line 39: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
space required after that close brace '}'
File src/mainboard/asus/p2b/irq_tables.c:
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
line over 96 characters
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
space required after that close brace '}'
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
line over 96 characters
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
space required after that close brace '}'
File src/mainboard/asus/p3b-f/irq_tables.c:
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x0c, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x0b, 0), {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x0a, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x09, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
line over 96 characters
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x0d, 0), {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0},
space required after that close brace '}'
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x0e, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0},
line over 96 characters
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x0e, 0), {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0},
space required after that close brace '}'
Patch Set #1, Line 39: {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
line over 96 characters
Patch Set #1, Line 39: {0x00, PCI_DEVFN(0x04, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
space required after that close brace '}'
Patch Set #1, Line 40: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
line over 96 characters
Patch Set #1, Line 40: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
space required after that close brace '}'
File src/mainboard/emulation/qemu-i440fx/irq_tables.c:
Patch Set #1, Line 30: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
line over 96 characters
Patch Set #1, Line 30: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0},
space required after that close brace '}'
Patch Set #1, Line 31: {0x00, PCI_DEVFN(0x02, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0},
line over 96 characters
Patch Set #1, Line 31: {0x00, PCI_DEVFN(0x02, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0},
space required after that close brace '}'
Patch Set #1, Line 32: {0x00, PCI_DEVFN(0x03, 0), {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 32: {0x00, PCI_DEVFN(0x03, 0), {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x04, 0), {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x04, 0), {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0x0def8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x05, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x05, 0), {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x06, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x06, 0), {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x5, 0x0},
space required after that close brace '}'
File src/mainboard/getac/p470/irq_tables.c:
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
space required after that close brace '}'
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
line over 96 characters
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
space required after that close brace '}'
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
line over 96 characters
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
space required after that close brace '}'
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
line over 96 characters
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
space required after that close brace '}'
Patch Set #1, Line 39: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
line over 96 characters
Patch Set #1, Line 39: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
space required after that close brace '}'
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
line over 96 characters
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
space required after that close brace '}'
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
line over 96 characters
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
space required after that close brace '}'
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
line over 96 characters
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
space required after that close brace '}'
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
line over 96 characters
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
space required after that close brace '}'
Patch Set #1, Line 47: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 47: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 48: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
line over 96 characters
Patch Set #1, Line 48: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
space required after that close brace '}'
Patch Set #1, Line 49: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 49: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 50: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
line over 96 characters
Patch Set #1, Line 50: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
space required after that close brace '}'
File src/mainboard/ibase/mb899/irq_tables.c:
Patch Set #1, Line 32: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
line over 96 characters
Patch Set #1, Line 32: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
space required after that close brace '}'
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
space required after that close brace '}'
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
line over 96 characters
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
space required after that close brace '}'
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
line over 96 characters
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
space required after that close brace '}'
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
line over 96 characters
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
space required after that close brace '}'
Patch Set #1, Line 39: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
line over 96 characters
Patch Set #1, Line 39: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
space required after that close brace '}'
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
line over 96 characters
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
space required after that close brace '}'
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
line over 96 characters
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
space required after that close brace '}'
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
line over 96 characters
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
space required after that close brace '}'
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 47: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053
line over 96 characters
Patch Set #1, Line 47: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet Marvell 88E8053
space required after that close brace '}'
Patch Set #1, Line 48: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 48: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 49: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
line over 96 characters
Patch Set #1, Line 49: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
space required after that close brace '}'
File src/mainboard/intel/d945gclf/irq_tables.c:
Patch Set #1, Line 32: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
line over 96 characters
Patch Set #1, Line 32: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
space required after that close brace '}'
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
space required after that close brace '}'
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
line over 96 characters
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
space required after that close brace '}'
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
line over 96 characters
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
space required after that close brace '}'
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
line over 96 characters
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
space required after that close brace '}'
Patch Set #1, Line 39: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
line over 96 characters
Patch Set #1, Line 39: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
space required after that close brace '}'
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
line over 96 characters
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
space required after that close brace '}'
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
line over 96 characters
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
space required after that close brace '}'
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
line over 96 characters
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
space required after that close brace '}'
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 47: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
line over 96 characters
Patch Set #1, Line 47: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
space required after that close brace '}'
Patch Set #1, Line 48: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 48: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 49: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
line over 96 characters
Patch Set #1, Line 49: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
space required after that close brace '}'
File src/mainboard/kontron/986lcd-m/irq_tables.c:
Patch Set #1, Line 32: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
line over 96 characters
Patch Set #1, Line 32: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
space required after that close brace '}'
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
space required after that close brace '}'
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
line over 96 characters
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
space required after that close brace '}'
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
line over 96 characters
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
space required after that close brace '}'
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
line over 96 characters
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
space required after that close brace '}'
Patch Set #1, Line 39: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
line over 96 characters
Patch Set #1, Line 39: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
space required after that close brace '}'
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
line over 96 characters
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
space required after that close brace '}'
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
line over 96 characters
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
space required after that close brace '}'
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
line over 96 characters
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
space required after that close brace '}'
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 47: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
line over 96 characters
Patch Set #1, Line 47: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
space required after that close brace '}'
Patch Set #1, Line 48: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 48: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 49: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
line over 96 characters
Patch Set #1, Line 49: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
space required after that close brace '}'
File src/mainboard/roda/rk886ex/irq_tables.c:
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
line over 96 characters
Patch Set #1, Line 33: {0x00, PCI_DEVFN(0x01, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
space required after that close brace '}'
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
line over 96 characters
Patch Set #1, Line 34: {0x00, PCI_DEVFN(0x02, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
space required after that close brace '}'
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
line over 96 characters
Patch Set #1, Line 35: {0x00, PCI_DEVFN(0x1e, 0), {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
space required after that close brace '}'
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
line over 96 characters
Patch Set #1, Line 36: {0x00, PCI_DEVFN(0x1f, 0), {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
space required after that close brace '}'
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
line over 96 characters
Patch Set #1, Line 37: {0x00, PCI_DEVFN(0x1d, 0), {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
space required after that close brace '}'
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
line over 96 characters
Patch Set #1, Line 38: {0x00, PCI_DEVFN(0x1b, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
space required after that close brace '}'
Patch Set #1, Line 39: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
line over 96 characters
Patch Set #1, Line 39: {0x00, PCI_DEVFN(0x1c, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
space required after that close brace '}'
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
line over 96 characters
Patch Set #1, Line 40: {0x04, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
space required after that close brace '}'
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
line over 96 characters
Patch Set #1, Line 41: {0x04, PCI_DEVFN(0x01, 0), {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
space required after that close brace '}'
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
line over 96 characters
Patch Set #1, Line 42: {0x04, PCI_DEVFN(0x02, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
space required after that close brace '}'
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
line over 96 characters
Patch Set #1, Line 43: {0x04, PCI_DEVFN(0x03, 0), {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
space required after that close brace '}'
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
line over 96 characters
Patch Set #1, Line 44: {0x04, PCI_DEVFN(0x04, 0), {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
space required after that close brace '}'
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
line over 96 characters
Patch Set #1, Line 45: {0x04, PCI_DEVFN(0x05, 0), {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
space required after that close brace '}'
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
line over 96 characters
Patch Set #1, Line 46: {0x04, PCI_DEVFN(0x06, 0), {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
space required after that close brace '}'
Patch Set #1, Line 47: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 47: {0x04, PCI_DEVFN(0x09, 0), {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 48: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
line over 96 characters
Patch Set #1, Line 48: {0x01, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
space required after that close brace '}'
Patch Set #1, Line 49: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
line over 96 characters
Patch Set #1, Line 49: {0x02, PCI_DEVFN(0, 0), {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
space required after that close brace '}'
Patch Set #1, Line 50: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
line over 96 characters
Patch Set #1, Line 50: {0x03, PCI_DEVFN(0, 0), {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
space required after that close brace '}'
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