Jonathan Zhang uploaded patch set #6 to this change.

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soc/intel/xeon_sp/skx: fix mem64 BAR assignment

PCIe End Point device's BARs need to be accomodated in bridge device's
resource base/limit config registers. In particular, mem32/mem64
(non-prefetchable) BARs need to be accomondated in bridge device's
mem base/limit config registers.

This patches fixes the bug that mem64 BAR is not considered when
setting bridge device's mem base/limit config registers.

Without this patch, TiogaPass without riser card works fine; but on
TiogaPass with riser card, the boot fails with MTRR table overflow.

TESTED=booted TiogaPass with PCIe riser card; Verified PCIe devices
works in target OS, and resource assignments are correct.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: Morgan_Jang@wiwynn.com
Tested-by: Ryback.Hung@quantatw.com
Change-Id: I8dd7d94d52ad02f22c8e69b2e5d6dde2a79bc1f7
---
M src/soc/intel/xeon_sp/skx/chip.c
1 file changed, 96 insertions(+), 96 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40500/6

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