Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18178
-gerrit
commit ce48213916fe367196b1674311ab638da14551ad Author: Lin Huang hl@rock-chips.com Date: Wed Jan 18 09:44:34 2017 +0800
rockchip/rk3399: set edp pclk to 25MHz
It may cause an edp aux transfer error if the edp pclk is set too high, so reduce it to 25MHz.
BUG=chrome-os-partner:60130 BRANCH=None TEST=Build and Boot
Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596 Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3 Original-Signed-off-by: Lin Huang hl@rock-chips.com Original-Reviewed-on: https://chromium-review.googlesource.com/429410 Original-Commit-Ready: Julius Werner jwerner@chromium.org Original-Tested-by: Julius Werner jwerner@chromium.org Original-Reviewed-by: Julius Werner jwerner@chromium.org --- src/soc/rockchip/rk3399/clock.c | 25 +++++++++++++++++++++++++ src/soc/rockchip/rk3399/display.c | 1 + src/soc/rockchip/rk3399/include/soc/clock.h | 1 + 3 files changed, 27 insertions(+)
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 383a761..eb413a1 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -181,6 +181,13 @@ enum { CLK_TSADC_DIV_CON_MASK = 0x3ff, CLK_TSADC_DIV_CON_SHIFT = 0,
+ /* CLKSEL_CON44 */ + CLK_PCLK_EDP_PLL_SEL_MASK = 1, + CLK_PCLK_EDP_PLL_SEL_SHIFT = 15, + CLK_PCLK_EDP_PLL_SEL_CPLL = 0, + CLK_PCLK_EDP_DIV_CON_MASK = 0x3f, + CLK_PCLK_EDP_DIV_CON_SHIFT = 8, + /* CLKSEL_CON47 & CLKSEL_CON48 */ ACLK_VOP_PLL_SEL_MASK = 0x3, ACLK_VOP_PLL_SEL_SHIFT = 6, @@ -838,3 +845,21 @@ int rkclk_was_watchdog_reset(void) /* Bits 5 and 4 are "second" and "first" global watchdog reset. */ return read32(&cru_ptr->glb_rst_st) & 0x30; } + +void rkclk_configure_edp(unsigned int hz) +{ + int src_clk_div; + + src_clk_div = CPLL_HZ / hz; + assert((src_clk_div - 1 <= 63) && (src_clk_div * hz == CPLL_HZ)); + + write32(&cru_ptr->clksel_con[44], + RK_CLRSETBITS(CLK_PCLK_EDP_PLL_SEL_MASK << + CLK_PCLK_EDP_PLL_SEL_SHIFT | + CLK_PCLK_EDP_DIV_CON_MASK << + CLK_PCLK_EDP_DIV_CON_SHIFT, + CLK_PCLK_EDP_PLL_SEL_CPLL << + CLK_PCLK_EDP_PLL_SEL_SHIFT | + (src_clk_div - 1) << + CLK_PCLK_EDP_DIV_CON_SHIFT)); +} diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 5199bf3..c7ca891 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -65,6 +65,7 @@ void rk_display_init(device_t dev) case VOP_MODE_EDP: printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); rkclk_configure_vop_aclk(vop_id, 200 * MHz); + rkclk_configure_edp(25 * MHz);
/* select edp signal from vop0 */ write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5)); diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 82bf215..3047f73 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -119,5 +119,6 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); int rkclk_was_watchdog_reset(void); uint32_t rkclk_i2c_clock_for_bus(unsigned bus); +void rkclk_configure_edp(unsigned int hz);
#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */