[coreboot-gerrit] [S] Change in coreboot[main]: arch/riscv/payload: Replace old RISC-V CSR names with their values

[Zebreus (Code Review)]

Zebreus has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79364?usp=email )

Change subject: arch/riscv/payload: Replace old RISC-V CSR names with their values
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arch/riscv/payload: Replace old RISC-V CSR names with their values

LLVM/clang 17 removed support for CSR names that are no longer included
in the RISC-V ISA Manual Privileged Specification since version 1.12.
Instead we now use the numerical values they represent directly. These
magic numbers can not be defined in macros because they will not get
expanded.

Related LLVM commit: https://reviews.llvm.org/D149278

Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132
Signed-off-by: Zebreus 
---
M src/arch/riscv/payload.c
1 file changed, 6 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79364/1

diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index 3097ad1..1cbf50a 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -41,10 +41,12 @@
    switch (payload_mode) {
    case RISCV_PAYLOAD_MODE_U:
    	status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U);
-		/* Trap vector base address point to the payload */
-		write_csr(utvec, doit);
-		/* disable U-Mode interrupt */
-		write_csr(uie, 0);
+		/* Trap vector base address point to the payload
+		0x0005 is the User trap handler base address register. */
+		write_csr(0x0005, doit);
+		/* disable U-Mode interrupt
+		0x0004 is the User interrupt-enable register. */
+		write_csr(0x0004, 0);
    	break;
    case RISCV_PAYLOAD_MODE_S:
    	status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);