Marshall Dawson has uploaded this change for review.

View Change

soc/amd/picasso: Update calculation for TSC frequency

Remove the Family 15h step of finding the number of boost states
and get the frequency directly out of the Pstate0 register.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I909743483309279eb8c3bf68852d6082381f0dff
---
M src/soc/amd/picasso/tsc_freq.c
1 file changed, 3 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33765/1

diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c
index 29121b9..2277b33 100644
--- a/src/soc/amd/picasso/tsc_freq.c
+++ b/src/soc/amd/picasso/tsc_freq.c
@@ -19,26 +19,16 @@
 #include <cpu/amd/msr.h>
 #include <cpu/x86/tsc.h>
 #include <console/console.h>
-#include <soc/pci_devs.h>
-#include <device/pci_ops.h>
 
 unsigned long tsc_freq_mhz(void)
 {
 	msr_t msr;
 	uint8_t cpufid;
 	uint8_t cpudid;
-	uint8_t boost_states;
+	uint8_t high_state;
 
-	/*
-	 * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for
-	 * MSR0000_0010.  The TSC increments at the P0 frequency. According
-	 * to the "Software P-state Numbering" section, P0 is the highest
-	 * non-boosted state.  freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
-	 */
-	boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL)
-			>> 2) & 0x7;
-
-	msr = rdmsr(PSTATE_0_MSR + boost_states);
+	high_state = rdmsr(PS_LIM_REG).lo & 0x7;
+	msr = rdmsr(PSTATE_0_MSR + high_state);
 	if (!(msr.hi & 0x80000000))
 		die("Unknown error: cannot determine P-state 0\n");
 

To view, visit change 33765. To unsubscribe, or for help writing mail filters, visit settings.