Patch Set 4:
My test results for KBL:
memsetting 1GiB of memory with different MTRR settings in NEM right after raminit:do_fsp_post_memory_init: took 9180 msec to clear 1GiB UC
do_fsp_post_memory_init: took 9179 msec to clear 1GiB WPROT
do_fsp_post_memory_init: took 39 msec to clear 1GiB WRCOMB
do_fsp_post_memory_init: took 76 msec to clear 1GiB WRBACK
Appreciate your help Patrick for the data using this CL and analysis.
The use of WRBACK in NEM causes postcar stage loading to fail.
yes, me and Aaron are debugging this issue with cache architect on CML (behavior should be same across), the symptoms that we are seeing is that "invd" is clearing LLC cache line completely when marked as WB but WP/WC doesn't create problem although "invd" should clear entire LLC cache line. As per our understanding this is expected behavior of WB cache vs other type. Hence we are working on alternative ways to achieve the same. We have some sight but still under debug.
The use of WRCOMB seems fine, it still boots.
yes, WC and WP will work for sure. verified that part.
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