Elyes HAOUAS has uploaded this change for review.
mainboard/msi/ms9185: Fix coding style
Change-Id: I3cca4adbf04edfd88a9b8ae52cf4d62d429e6c45
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/mainboard/msi/ms9185/mptable.c
M src/mainboard/msi/ms9185/romstage.c
2 files changed, 11 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/23536/1
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index e93602b..e90fd54 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -54,7 +54,7 @@
{
device_t dev = 0;
struct resource *res;
- for(i = 0; i < 3; i++) {
+ for (i = 0; i < 3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -80,9 +80,8 @@
//USB
outb(0x01, 0xc00); outb(0x0a, 0xc01);
- for(i = 0; i < 3; i++) {
+ for (i = 0; i < 3; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
- }
@@ -91,7 +90,7 @@
{
device_t dev;
dev = dev_find_device(0x1166, 0x0205, 0);
- if(dev) {
+ if (dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
dword |= (1 << 4); // enable interrupts
@@ -101,46 +100,39 @@
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
// AIC 8130 Galileo Technology...
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6 << 2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
- }
//pci slot (on bcm5785)
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5 << 2)|i, m->apicid_bcm5785[1], 8+i%4); //
- }
//onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4 << 2)|0, m->apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4 << 2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
- }
//onboard Broadcom
- for(i = 0; i < 2; i++) {
+ for (i = 0; i < 2; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4 << 2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
- }
// First PCI-E x8
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0 << 2)|i, m->apicid_bcm5785[1], 0xe); //
- }
// Second PCI-E x8
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0 << 2)|i, m->apicid_bcm5785[1], 0xc); //
- }
// Third PCI-E x1
- for(i = 0; i < 4; i++) {
+ for (i = 0; i < 4; i++)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0 << 2)|i, m->apicid_bcm5785[1], 0xd); //
- }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index a86b57a..e509529 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -181,7 +181,7 @@
#if 0
int i;
- for(i = 0; i < 2; i++) {
+ for (i = 0; i < 2; i++) {
activate_spd_rom(sysinfo->ctrl+i);
dump_smbus_registers();
}
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