Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510
-gerrit
commit a36bc5f21b9c6c7b30530ccdacfe61a525096883 Author: Aaron Durbin adurbin@chromium.org Date: Fri Sep 4 12:06:05 2015 -0500
x86: link romstage like the other architectures
All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency.
BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin adubin@chromium.org --- src/arch/x86/Makefile.inc | 7 +++-- src/arch/x86/include/arch/header.ld | 6 +++++ src/arch/x86/include/arch/memlayout.h | 13 ++++++++- src/arch/x86/romstage.ld | 50 +++++++++-------------------------- src/cpu/x86/32bit/entry32.ld | 1 - src/lib/Makefile.inc | 4 +-- 6 files changed, 35 insertions(+), 46 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7337f1e..4c88a27 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
-romstage-srcs += $(src)/arch/x86/romstage.ld -romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld +romstage-y += romstage.ld
# Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat)
-$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - cat $^ >> $@.tmp + cat $< >> $@.tmp mv $@.tmp $@
$(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index dd6cb27..55547ad 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -17,9 +17,15 @@ * Foundation, Inc. */
+#include <rules.h> + PHDRS { to_load PT_LOAD; }
+#if ENV_RAMSTAGE ENTRY(_start) +#elif ENV_ROMSTAGE +ENTRY(protected_start) +#endif diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 54b8b4a..abaa8c7 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -20,6 +20,17 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H
-/* Currently empty to satisfy common arch requirements. */ +#include <rules.h> + +#if ENV_ROMSTAGE +/* Ensure the binding for .rom sections comes prior to all other text. */ +#define ARCH_FIRST_TEXT \ + *(.rom.text); \ + *(.rom.data); + +/* No .data or .bss in romstage. Cache as ram is handled separately. */ +#define ARCH_STAGE_HAS_DATA_SECTION 0 +#define ARCH_STAGE_HAS_BSS_SECTION 0 +#endif
#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index cc0142e..9c44b13 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,52 +19,25 @@ * Foundation, Inc. */
-TARGET(binary) +#include <memlayout.h> +#include <arch/header.ld> + SECTIONS { - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.text); - *(.text.*); - . = ALIGN(4); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M)
. = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { - _car_data_start = .; + SYMBOL_CURRENT_LOC(car_data_start) #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - _timestamp = .; - . = . + 0x100; - _etimestamp = .; + TIMESTAMP(., 0x100) #endif *(.car.global_data); - _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents. - * However, collisions within the cache-as-ram region cannot be - * statically checked because the cache-as-ram region usage is - * cpu/chipset dependent. */ - _preram_cbmem_console = .; - _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) }
/* Global variables are not allowed in romstage diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld deleted file mode 100644 index 471b5f7..0000000 --- a/src/cpu/x86/32bit/entry32.ld +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4aa6bf8..464d631 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -192,12 +192,12 @@ smm-y += halt.c secmon-y += halt.c
ifneq ($(CONFIG_ARCH_X86),y) -# X86 bootblock and romstage use custom ldscripts that are all glued together, +# X86 bootblock uses custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well bootblock-y += program.ld -romstage-y += program.ld endif
+romstage-y += program.ld ramstage-y += program.ld
ifeq ($(CONFIG_RELOCATABLE_MODULES),y)