Subrata Banik submitted this change.
mb/intel/adlrvp: Update GPIOs as per latest schematics
1. GPP_D8, GPP_H23 => Remove unused GPIOs
2. GPP_E18 .. GPP_E22 => Program the correct Native Functions for GPIO
Change-Id: Iedb1f8fbf5f96a9617b72ba1a6419e3fd4e331b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49260
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/intel/adlrvp/gpio.c
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 1943a66..3131cc0 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -243,16 +243,16 @@
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ PAD_NC(GPP_D8, NONE),
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */
- PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
@@ -265,7 +265,7 @@
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1),
+ PAD_NC(GPP_H23, NONE),
/* A21 : HDMI CRLS CTRLCLK */
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
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