Patrick Rudolph has uploaded this change for review.
cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode
* Use heap for linker script calculated constant to fix relocation
symbols in mixed assembly code.
* Work around a strange bug that causes the CPU to halt when accessing
MMX registers in long mode
Tested on HPZ220:
* Still boots in x86_32.
Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/cpu/intel/car/non-evict/cache_as_ram.S
1 file changed, 40 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44673/1
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index b24f101..481cbee 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -9,6 +9,27 @@
.global bootblock_pre_c_entry
+/* Trick the linker into supporting x86_64 relocations in 32bit code */
+#ifdef __x86_64__
+rom_mtrr_mask:
+.quad _rom_mtrr_mask
+
+rom_mtrr_base:
+.quad _rom_mtrr_base
+
+car_mtrr_mask:
+.quad _car_mtrr_mask
+#else
+rom_mtrr_mask:
+.long _rom_mtrr_mask
+
+rom_mtrr_base:
+.long _rom_mtrr_base
+
+car_mtrr_mask:
+.long _car_mtrr_mask
+#endif
+
.code32
_cache_as_ram_setup:
@@ -83,7 +104,6 @@
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
-
post_code(0x23)
/* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx
@@ -96,20 +116,20 @@
/* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
- movl $_car_mtrr_mask, %eax
+ mov car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
- movl $_rom_mtrr_base, %eax
+ mov rom_mtrr_base, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
- movl $_rom_mtrr_mask, %eax
+ mov rom_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
@@ -208,17 +228,24 @@
the pushes below. */
andl $0xfffffff0, %esp
- /* entry64.inc preserves ebx. */
+#ifdef __x86_64__
+ /*
+ * BUG: On some x86 platforms acessing MMX register in long mode
+ * causes a crash. Retrieve them here and then switch to long mode.
+ */
+ movd %mm2, %eax
+ push %eax
+ movd %mm1, %eax /* tsc */
+ push %eax
+ movd %mm0, %eax
+ push %eax
+ xorl %eax, %eax
+ push %eax /* BIST */
+
#include <cpu/x86/64bit/entry64.inc>
-#ifdef __x86_64__
-
- movd %mm2, %rdi
- shld %rdi, 32
- movd %mm1, %rsi
- or %rsi, %rdi /* tsc */
-
- movd %mm0, %rsi /* BIST */
+ pop %rsi /* BIST */
+ pop %rdi /* tsc */
#else
subl $4, %esp
/* push TSC and BIST to stack */
To view, visit change 44673. To unsubscribe, or for help writing mail filters, visit settings.