Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7962
-gerrit
commit 599b7284489e1fcb53646f9a217b1c85676e4803 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Dec 27 21:04:53 2014 +0200
haswell: Fix MRC cache to use CBFS
Place the mrc.cache file at top of CBFS. There is no real requirement for it to have a fixed location though.
Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/northbridge/intel/haswell/Kconfig | 10 ---------- src/northbridge/intel/haswell/Makefile.inc | 12 ++++++++++++ src/northbridge/intel/haswell/mrccache.c | 12 +++++------- 3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index cac5c46..0845a3f 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -42,16 +42,6 @@ config CACHE_MRC_SIZE_KB int default 512
-# FIXME: build from rom size -config MRC_CACHE_BASE - hex - default 0xff800000 - -config MRC_CACHE_LOCATION - hex - depends on !CHROMEOS - default 0x370000 - config MRC_CACHE_SIZE hex depends on !CHROMEOS diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index f2577c7..c8ebcdb 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -40,3 +40,15 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 mrc.bin-type := 0xab
+ifneq ($(CONFIG_CHROMEOS),y) +$(obj)/mrc.cache: $(obj)/config.h + dd if=/dev/zero count=1 \ + bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ + tr '\000' '\377' > $@ + +cbfs-files-y += mrc.cache +mrc.cache-file := $(obj)/mrc.cache +mrc.cache-position := 0xfffe0000 +mrc.cache-type := 0xac +endif + diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index a921e04..540bbf6 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -66,16 +66,14 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) */ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u32 region_size; #if CONFIG_CHROMEOS - region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); + return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); #else - region_size = CONFIG_MRC_CACHE_SIZE; - *mrc_region_ptr = (struct mrc_data_container *) - (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); -#endif - + size_t region_size; + *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + "mrc.cache", 0xac, ®ion_size); return region_size; +#endif }
/*