Angel Pons submitted this change.
haswell boards: Correct USB config indentation
Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/asrock/b85m_pro4/romstage.c
M src/mainboard/asrock/h81m-hds/romstage.c
M src/mainboard/google/beltino/romstage.c
M src/mainboard/google/slippy/variants/falco/romstage.c
M src/mainboard/google/slippy/variants/leon/romstage.c
M src/mainboard/google/slippy/variants/peppy/romstage.c
M src/mainboard/google/slippy/variants/wolf/romstage.c
M src/mainboard/hp/folio_9480m/romstage.c
M src/mainboard/intel/baskingridge/romstage.c
M src/mainboard/lenovo/t440p/romstage.c
M src/mainboard/msi/h81m-p33/romstage.c
M src/mainboard/supermicro/x10slm-f/romstage.c
12 files changed, 314 insertions(+), 314 deletions(-)
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index 16f3d0a..1c17fcb 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -25,29 +25,29 @@
spd_map[3] = 0xa6;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- { 1, 0 },
- { 1, 0 },
- { 1, 1 },
- { 1, 1 },
- { 1, 2 },
- { 1, 2 },
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ { 1, 0 },
+ { 1, 0 },
+ { 1, 1 },
+ { 1, 1 },
+ { 1, 2 },
+ { 1, 2 },
+};
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index b8ecd43..16b1500 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -23,30 +23,30 @@
spd_map[2] = 0xa4;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 0 },
- { 1, 0 },
- { 0, USB_OC_PIN_SKIP },
- { 0, USB_OC_PIN_SKIP },
- { 0, USB_OC_PIN_SKIP },
- { 0, USB_OC_PIN_SKIP },
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 },
+ { 1, 0 },
+ { 0, USB_OC_PIN_SKIP },
+ { 0, USB_OC_PIN_SKIP },
+ { 0, USB_OC_PIN_SKIP },
+ { 0, USB_OC_PIN_SKIP },
+};
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index f009f5a..dda2edc 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -46,30 +46,30 @@
spd_map[2] = 0xa4;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0064, 1, 0, /* P0: VP8 */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, 0, /* P1: Port A, CN22 */
- USB_PORT_INTERNAL },
- { 0x0040, 1, 1, /* P2: Port B, CN23 */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */
- USB_PORT_INTERNAL },
- { 0x0040, 1, 2, /* P4: Port C, CN25 */
- USB_PORT_INTERNAL },
- { 0x0040, 1, 2, /* P5: Port D, CN25 */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */
- USB_PORT_INTERNAL },
- { 0x0000, 0, 0, /* P7: N/C */
- USB_PORT_SKIP },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0064, 1, 0, /* P0: VP8 */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 0, /* P1: Port A, CN22 */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, 1, /* P2: Port B, CN23 */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, 2, /* P4: Port C, CN25 */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, 2, /* P5: Port D, CN25 */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */
+ USB_PORT_INTERNAL },
+ { 0x0000, 0, 0, /* P7: N/C */
+ USB_PORT_SKIP },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; CN22 */
- { 1, 1 }, /* P2; CN23 */
- { 1, 2 }, /* P3; CN25 */
- { 1, 2 }, /* P4; CN25 */
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 }, /* P1; CN22 */
+ { 1, 1 }, /* P2; CN23 */
+ { 1, 2 }, /* P3; CN25 */
+ { 1, 2 }, /* P4; CN25 */
+};
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c
index de0ac76..8870fae 100644
--- a/src/mainboard/google/slippy/variants/falco/romstage.c
+++ b/src/mainboard/google/slippy/variants/falco/romstage.c
@@ -48,30 +48,30 @@
}
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0064, 1, 0, /* P0: Port A, CN8 */
- USB_PORT_BACK_PANEL },
- { 0x0052, 1, 0, /* P1: Port B, CN9 */
- USB_PORT_BACK_PANEL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
- USB_PORT_INTERNAL },
- { 0x0123, 1, 3, /* P7: USB2 Port */
- USB_PORT_INTERNAL },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0064, 1, 0, /* P0: Port A, CN8 */
+ USB_PORT_BACK_PANEL },
+ { 0x0052, 1, 0, /* P1: Port B, CN9 */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
+ USB_PORT_INTERNAL },
+ { 0x0123, 1, 3, /* P7: USB2 Port */
+ USB_PORT_INTERNAL },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; Port A, CN8 */
- { 1, 0 }, /* P2; Port B, CN9 */
- { 0, USB_OC_PIN_SKIP }, /* P3; */
- { 0, USB_OC_PIN_SKIP }, /* P4; */
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 }, /* P1; Port A, CN8 */
+ { 1, 0 }, /* P2; Port B, CN9 */
+ { 0, USB_OC_PIN_SKIP }, /* P3; */
+ { 0, USB_OC_PIN_SKIP }, /* P4; */
+};
diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c
index daf0c16..49961d9 100644
--- a/src/mainboard/google/slippy/variants/leon/romstage.c
+++ b/src/mainboard/google/slippy/variants/leon/romstage.c
@@ -44,30 +44,30 @@
spd_file + (spd_index * spd_len), spd_len);
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, /* P0: Port A, CN10 */
- USB_PORT_BACK_PANEL },
- { 0x0040, 1, 2, /* P1: Port B, CN11 */
- USB_PORT_BACK_PANEL },
- { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
- USB_PORT_MINI_PCIE },
- { 0x0080, 1, USB_OC_PIN_SKIP, /* P4: SD Card */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: LTE */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SIM CARD */
- USB_PORT_FLEX },
- { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
- USB_PORT_SKIP },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, /* P0: Port A, CN10 */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, /* P1: Port B, CN11 */
+ USB_PORT_BACK_PANEL },
+ { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+ USB_PORT_MINI_PCIE },
+ { 0x0080, 1, USB_OC_PIN_SKIP, /* P4: SD Card */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P5: LTE */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SIM CARD */
+ USB_PORT_FLEX },
+ { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
+ USB_PORT_SKIP },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; Port A, CN10 */
- { 1, 2 }, /* P2; Port B, CN11 */
- { 0, USB_OC_PIN_SKIP }, /* P3; */
- { 0, USB_OC_PIN_SKIP }, /* P4; */
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 }, /* P1; Port A, CN10 */
+ { 1, 2 }, /* P2; Port B, CN11 */
+ { 0, USB_OC_PIN_SKIP }, /* P3; */
+ { 0, USB_OC_PIN_SKIP }, /* P4; */
+};
diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c
index 535c07b..8a3486a 100644
--- a/src/mainboard/google/slippy/variants/peppy/romstage.c
+++ b/src/mainboard/google/slippy/variants/peppy/romstage.c
@@ -62,30 +62,30 @@
}
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, 0, /* P1: Port A, CN10 */
- USB_PORT_BACK_PANEL },
- { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, 2, /* P4: Port B, CN6 */
- USB_PORT_BACK_PANEL },
- { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
- USB_PORT_SKIP },
- { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
- USB_PORT_FLEX },
- { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
- USB_PORT_SKIP },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 0, /* P1: Port A, CN10 */
+ USB_PORT_BACK_PANEL },
+ { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 2, /* P4: Port B, CN6 */
+ USB_PORT_BACK_PANEL },
+ { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
+ USB_PORT_SKIP },
+ { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
+ USB_PORT_FLEX },
+ { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
+ USB_PORT_SKIP },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; Port A, CN6 */
- { 0, USB_OC_PIN_SKIP }, /* P2; */
- { 0, USB_OC_PIN_SKIP }, /* P3; */
- { 0, USB_OC_PIN_SKIP }, /* P4; */
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 }, /* P1; Port A, CN6 */
+ { 0, USB_OC_PIN_SKIP }, /* P2; */
+ { 0, USB_OC_PIN_SKIP }, /* P3; */
+ { 0, USB_OC_PIN_SKIP }, /* P4; */
+};
diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c
index 40ff9c2..9080f46 100644
--- a/src/mainboard/google/slippy/variants/wolf/romstage.c
+++ b/src/mainboard/google/slippy/variants/wolf/romstage.c
@@ -48,30 +48,30 @@
}
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, /* P0: Port A, CN10 */
- USB_PORT_BACK_PANEL },
- { 0x0040, 1, 2, /* P1: Port B, CN11 */
- USB_PORT_BACK_PANEL },
- { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
- USB_PORT_INTERNAL },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
- USB_PORT_INTERNAL },
- { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */
- USB_PORT_SKIP },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
- USB_PORT_INTERNAL },
- { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
- USB_PORT_SKIP },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, /* P0: Port A, CN10 */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, /* P1: Port B, CN11 */
+ USB_PORT_BACK_PANEL },
+ { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
+ USB_PORT_INTERNAL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
+ USB_PORT_INTERNAL },
+ { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */
+ USB_PORT_SKIP },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
+ USB_PORT_INTERNAL },
+ { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
+ USB_PORT_SKIP },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; Port A, CN10 */
- { 1, 2 }, /* P2; Port B, CN11 */
- { 0, USB_OC_PIN_SKIP }, /* P3; */
- { 0, USB_OC_PIN_SKIP }, /* P4; */
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 }, /* P1; Port A, CN10 */
+ { 1, 2 }, /* P2; Port B, CN11 */
+ { 0, USB_OC_PIN_SKIP }, /* P3; */
+ { 0, USB_OC_PIN_SKIP }, /* P4; */
+};
diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c
index 0c4308b..496005d 100644
--- a/src/mainboard/hp/folio_9480m/romstage.c
+++ b/src/mainboard/hp/folio_9480m/romstage.c
@@ -23,21 +23,21 @@
spd_map[2] = 0xa4;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */
- { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */
- { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */
- { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */
+ { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */
+ { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */
+ { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- { 1, USB_OC_PIN_SKIP }, /* dock */
- { 1, USB_OC_PIN_SKIP }, /* left */
- { 1, USB_OC_PIN_SKIP }, /* right */
- { 0, USB_OC_PIN_SKIP },
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ { 1, USB_OC_PIN_SKIP }, /* dock */
+ { 1, USB_OC_PIN_SKIP }, /* left */
+ { 1, USB_OC_PIN_SKIP }, /* right */
+ { 0, USB_OC_PIN_SKIP },
+};
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 9c4c9b7..dc1f50f 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -49,44 +49,44 @@
spd_map[3] = 0xa6;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
- USB_PORT_BACK_PANEL },
- { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */
- USB_PORT_BACK_PANEL },
- { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */
- USB_PORT_FLEX },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */
- USB_PORT_DOCK },
- { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */
- USB_PORT_MINI_PCIE },
- { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */
- USB_PORT_FLEX },
- { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */
- USB_PORT_FRONT_PANEL },
- { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
- USB_PORT_FRONT_PANEL },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */
+ USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */
+ USB_PORT_FLEX },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */
+ USB_PORT_DOCK },
+ { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */
+ USB_PORT_MINI_PCIE },
+ { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */
+ USB_PORT_FLEX },
+ { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */
+ USB_PORT_FRONT_PANEL },
+ { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
+ USB_PORT_FRONT_PANEL },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 0 }, /* P1; */
- { 1, 0 }, /* P2; */
- { 1, 0 }, /* P3; */
- { 1, 0 }, /* P4; */
- { 1, 0 }, /* P6; */
- { 1, 0 }, /* P6; */
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 }, /* P1; */
+ { 1, 0 }, /* P2; */
+ { 1, 0 }, /* P3; */
+ { 1, 0 }, /* P4; */
+ { 1, 0 }, /* P6; */
+ { 1, 0 }, /* P6; */
+};
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c
index eaee734..7aca7c5 100644
--- a/src/mainboard/lenovo/t440p/romstage.c
+++ b/src/mainboard/lenovo/t440p/romstage.c
@@ -46,29 +46,29 @@
spd_map[2] = 0xa2;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
- { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
- { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK },
- { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */
- { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* WWAN */
- { 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */
- { 0x0080, 1, 6, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
+ { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK },
+ { 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* WWAN */
+ { 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */
+ { 0x0080, 1, 6, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- { 1, 0 },
- { 1, 0 },
- { 1, USB_OC_PIN_SKIP },
- { 1, USB_OC_PIN_SKIP },
- { 1, 1 },
- { 1, 1 }, /* WWAN */
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ { 1, 0 },
+ { 1, 0 },
+ { 1, USB_OC_PIN_SKIP },
+ { 1, USB_OC_PIN_SKIP },
+ { 1, 1 },
+ { 1, 1 }, /* WWAN */
+};
diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c
index 56c77cd..9bcb400 100644
--- a/src/mainboard/msi/h81m-p33/romstage.c
+++ b/src/mainboard/msi/h81m-p33/romstage.c
@@ -23,29 +23,29 @@
spd_map[2] = 0xa4;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
- { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- { 1, 0 },
- { 1, 0 },
- { 1, 1 },
- { 1, 1 },
- { 1, 2 },
- { 1, 2 },
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ { 1, 0 },
+ { 1, 0 },
+ { 1, 1 },
+ { 1, 1 },
+ { 1, 2 },
+ { 1, 2 },
+};
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index a2798d9..36f79a3 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -25,30 +25,30 @@
spd_map[3] = 0xa6;
}
- const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, USB_PORT_INTERNAL },
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0110, 1, 1, USB_PORT_BACK_PANEL },
- { 0x0110, 1, 1, USB_PORT_BACK_PANEL },
- { 0x0110, 1, 2, USB_PORT_BACK_PANEL },
- { 0x0110, 1, 2, USB_PORT_BACK_PANEL },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
- };
+const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, USB_PORT_INTERNAL },
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0110, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0110, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0110, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0110, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+};
- const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
- /* Enable, OCn# */
- { 1, 1 },
- { 1, 1 },
- { 0, USB_OC_PIN_SKIP },
- { 0, USB_OC_PIN_SKIP },
- { 1, 3 },
- { 1, 3 },
- };
+const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 1 },
+ { 1, 1 },
+ { 0, USB_OC_PIN_SKIP },
+ { 0, USB_OC_PIN_SKIP },
+ { 1, 3 },
+ { 1, 3 },
+};
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