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• File src/mainboard/google/brox/variants/baseboard/brox/ramstage.c:

  • Patch Set #2, Line 161: soc_config->tdp_pl4 -= POWER_LIMIT_TUNE;

    Are you adjusting twice for PL4 - especially when PL4 > PL3? PL3 got adjusted in line 151. […]

    Yes this intentional .It is recommended that Psyspl3 is set above psyspl2 by 1 or 2 Low PL4 does not cause functional failure but result in a loss in max obtainable frequency .A lower PL4 ensures that going lower than battery min voltage is prevented

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