Tim Wawrzynczak submitted this change.

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Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Caveh Jalali: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
soc/intel/tigerlake: Update Tiger Lake SA IDs

This patch updates Tiger Lake SA DID and report platform. According to
doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below
definitions of SA ID for TGL-UP4 skus:
TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h
TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h

Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/systemagent.c
4 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 62220d8..94ad02f 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3521,10 +3521,10 @@
#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
#define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
-#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14
-#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04
-#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10
+#define PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2 0x9A14
+#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02
+#define PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12
#define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532
#define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
#define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index e6bbfc7..72d611a 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -390,10 +390,10 @@
PCI_DEVICE_ID_INTEL_CML_H,
PCI_DEVICE_ID_INTEL_CML_H_4_2,
PCI_DEVICE_ID_INTEL_CML_H_8_2,
- PCI_DEVICE_ID_INTEL_TGL_ID_U,
- PCI_DEVICE_ID_INTEL_TGL_ID_U_1,
PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2,
- PCI_DEVICE_ID_INTEL_TGL_ID_Y,
+ PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2,
+ PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2,
+ PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2,
PCI_DEVICE_ID_INTEL_JSL_EHL,
PCI_DEVICE_ID_INTEL_EHL_ID_1,
PCI_DEVICE_ID_INTEL_JSL_ID_1,
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c
index 55a9790..6acc0c3 100644
--- a/src/soc/intel/tigerlake/bootblock/report_platform.c
+++ b/src/soc/intel/tigerlake/bootblock/report_platform.c
@@ -32,10 +32,10 @@
u16 mchid;
const char *name;
} mch_table[] = {
- { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" },
- { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" },
{ PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" },
- { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" },
+ { PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2, "Tigerlake-U-4-2" },
+ { PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2, "Tigerlake-Y-2-2" },
+ { PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2, "Tigerlake-Y-4-2" },
};

static struct {
diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c
index e428365..fd611bb 100644
--- a/src/soc/intel/tigerlake/systemagent.c
+++ b/src/soc/intel/tigerlake/systemagent.c
@@ -78,13 +78,12 @@
* differentiated here based on SA PCI ID.
*/
switch (sa_pci_id) {
- case PCI_DEVICE_ID_INTEL_TGL_ID_U:
- case PCI_DEVICE_ID_INTEL_TGL_ID_U_1:
- soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE];
- break;
case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2:
soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE];
break;
+ case PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2:
+ soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE];
+ break;
default:
printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
"configuration\n", sa_pci_id);

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763
Gerrit-Change-Number: 43061
Gerrit-PatchSet: 15
Gerrit-Owner: Derek Huang <derek.huang@intel.corp-partner.google.com>
Gerrit-Reviewer: Caveh Jalali <caveh@chromium.org>
Gerrit-Reviewer: Kane Chen <kane.chen@intel.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: David Wu <david_wu@quanta.corp-partner.google.com>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged