Attention is currently required from: Ashish Kumar Mishra, Saurabh Mishra, Subrata Banik.
2 comments:
Commit Message:
The memcpy impl. for
x86_64 changed to 8 byte copy and due to 4 byte limit, spi rw fails. MRC
cache rw regression observed in existing X86_64 platforms. Hence update
rw ops to use read32p/write32p.
Maybe change this to say that the hardware only accepts at most dword transactions at most which won't work with the current 64bit implementation of memcpy?
File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:
const uint8_t *byte_ptr = (const uint8_t *)data;
size_t bytes_to_copy;
union {
uint32_t full;
uint8_t bytes[4];
} dword;
for (size_t i = 0; i < len; i += 4) {
dword.full = 0;
bytes_to_copy = (len - i < 4) ? len - i : 4;
for (size_t j = 0; j < bytes_to_copy; j++)
dword.bytes[j] = byte_ptr[i + j];
write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full);
}
I think the HW accepts at most dword transactions, but also word and byte ones. Which is why the 32bit memcpy worked.
This code isn't efficient. Just loop over dwords and put them into SPIBAR_FDATA, then for the remaining bytes do it bytewise (just like 32bit memcpy)?
To view, visit change 82079. To unsubscribe, or for help writing mail filters, visit settings.