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1 comment:
File src/mainboard/erying/tgl/devicetree.cb:
Patch Set #7, Line 125: device ref pch_espi on
I wasn't sure how to configure it to be perfectly honest. […]
In Intel PCH, the I/O Range is configured using registers in the LPC/eSPI controller:
```
eSPI Generic I/O Range 1 (ESPI_LGIR1)
eSPI Generic I/O Range 2 (ESPI_LGIR2)
eSPI Generic I/O Range 3 (ESPI_LGIR3)
eSPI Generic I/O Range 4 (ESPI_LGIR4)
```
You can make a dump and check their values with the vendor's firmware to set the corresponding `genX_dec` values in the devicetree.
My point is, its probable that some of the EC/HWM registers are unavailable because of the incorrect IO range. But this is just a guess.
There was a similar problem on the asrock board (an example for nuvoton HWM - https://github.com/coreboot/coreboot/blob/main/src/mainboard/asrock/h110m/devicetree.cb#L146), which was resolved by this way. However, in your case, ITE makes the issue more difficult.
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