Subrata Banik has uploaded this change for review.

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include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN

Rename and updated POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f
to make the ramstage postcodes appear in an incremental order.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba
---
M src/include/console/post_codes.h
M src/lib/hardwaremain.c
2 files changed, 9 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52947/1

diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 9682e4d..29d2a79 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -112,6 +112,14 @@
 #define POST_PRE_HARDWAREMAIN			0x6e
 
 /**
+ * \brief Entry into coreboot in RAM stage main()
+ *
+ * This is the first call in hardwaremain.c. If this code is POSTed, then
+ * ramstage has successfully loaded and started executing.
+ */
+#define POST_ENTRY_HARDWAREMAIN		0x6f
+
+/**
  * \brief Before Device Probe
  *
  * Boot State Machine: bs_pre_device()
@@ -196,14 +204,6 @@
 #define POST_BS_PAYLOAD_BOOT			0x7b
 
 /**
- * \brief Entry into coreboot in RAM stage main()
- *
- * This is the first call in hardwaremain.c. If this code is POSTed, then
- * ramstage has successfully loaded and started executing.
- */
-#define POST_ENTRY_RAMSTAGE                     0x80
-
-/**
  * \brief Before calling FSP Notify before End of Firmware
  *
  * Going to call into FSP binary for Notify phase
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 895a942..cd4a57e 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -442,7 +442,7 @@
 	cbmem_initialize();
 
 	timestamp_add_now(TS_START_RAMSTAGE);
-	post_code(POST_ENTRY_RAMSTAGE);
+	post_code(POST_ENTRY_HARDWAREMAIN);
 
 	/* Handoff sleep type from romstage. */
 	acpi_is_wakeup_s3();

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