Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7549
-gerrit
commit 56b825b83ff6a5031665de93703e827b82f78be5 Author: Vladimir Serbinenko phcoder@gmail.com Date: Wed Nov 19 19:59:56 2014 +0100
i945: Merge romstage main().
main() is pretty similar on all i945 boards.
Main differences after this change: * mobo supplies standard hooks to do one thing at specific romstage point * instead of supplying a SPD map mainboard supplies an SPD retrieval function with standard library function to get SPD from one EEPROM. This allows to support machines like Acer Aspire One which have no EEPROM for soldered RAM. * PCI reset is controlled by Kconfig * Artec dongle init is controlled by Kconfig. Probably should be always done but I have no hardware to test.
Change-Id: Iecae53a9e9e2183377fcd760641894f810e40118 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/apple/macbook21/Kconfig | 1 + src/mainboard/apple/macbook21/early_mainboard.h | 3 - src/mainboard/apple/macbook21/early_southbridge.c | 10 +- src/mainboard/apple/macbook21/romstage.c | 104 +--------------- src/mainboard/getac/p470/romstage.c | 111 +++++------------ src/mainboard/ibase/mb899/romstage.c | 92 ++++---------- src/mainboard/intel/d945gclf/romstage.c | 67 ++--------- src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/kontron/986lcd-m/romstage.c | 113 +++++------------ src/mainboard/lenovo/t60/Kconfig | 2 + src/mainboard/lenovo/t60/romstage.c | 140 +++++++--------------- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/romstage.c | 129 +++++--------------- src/mainboard/roda/rk886ex/Kconfig | 2 + src/mainboard/roda/rk886ex/romstage.c | 121 +++++-------------- src/northbridge/intel/i945/Kconfig | 4 + src/northbridge/intel/i945/early_init.c | 87 ++++++++++++++ src/northbridge/intel/i945/raminit.c | 139 ++++++++++----------- src/northbridge/intel/i945/raminit.h | 12 +- 19 files changed, 378 insertions(+), 761 deletions(-)
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig index 8fd5f90..06188fd 100644 --- a/src/mainboard/apple/macbook21/Kconfig +++ b/src/mainboard/apple/macbook21/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select VGA select MAINBOARD_DO_EDID select INTEL_EDID + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET
config MAINBOARD_DIR string diff --git a/src/mainboard/apple/macbook21/early_mainboard.h b/src/mainboard/apple/macbook21/early_mainboard.h deleted file mode 100644 index 6c9dbe9..0000000 --- a/src/mainboard/apple/macbook21/early_mainboard.h +++ /dev/null @@ -1,3 +0,0 @@ -void ich7_enable_lpc(void); -void rcba_config(void); -void early_ich7_init(void); diff --git a/src/mainboard/apple/macbook21/early_southbridge.c b/src/mainboard/apple/macbook21/early_southbridge.c index 7e7b5a9..70a9dbd 100644 --- a/src/mainboard/apple/macbook21/early_southbridge.c +++ b/src/mainboard/apple/macbook21/early_southbridge.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "northbridge/intel/i945/i945.h" #include "southbridge/intel/i82801gx/i82801gx.h" -#include "early_mainboard.h" +#include "northbridge/intel/i945/raminit.h"
void setup_ich7_gpios(void) { @@ -251,3 +251,11 @@ void early_ich7_init(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } + +void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); +} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 4ec240d..2997587 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -1,103 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle svens@stackframe.org - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - -#include <stdint.h> -#include <string.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <cpu/intel/romstage.h> -#include <cpu/x86/lapic.h> -#include <timestamp.h> -#include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "early_mainboard.h" - -void main(unsigned long bist) -{ - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); -} +/* dummy */ diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 32323bc..f9da4fe 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -30,8 +30,6 @@ #include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -81,26 +79,6 @@ void setup_ich7_gpios(void) outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ }
-static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); - // Enable 0x02e0 - 0x2ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); - // Enable 0x600 - 0x6ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); - // Enable 0x68 - 0x6f - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); -} - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -170,7 +148,29 @@ static void early_superio_config(void) pnp_exit_ext_func_mode(dev); }
-static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); + // Enable 0x02e0 - 0x2ff + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x001c02e1); + // Enable 0x600 - 0x6ff + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); + // Enable 0x68 - 0x6f + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + + early_superio_config(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -194,7 +194,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; }
-static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -248,63 +248,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; }
-#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - -#if 0 - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); -#endif - - ich7_enable_lpc(); - early_superio_config(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 6f3e943..3c26d89 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -32,8 +32,6 @@ #include <superio/winbond/w83627ehg/w83627ehg.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -57,20 +55,6 @@ void setup_ich7_gpios(void) outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ }
-static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); - // Enable HWM at 0x290 - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); -} - /* This box has one superio * Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. @@ -142,7 +126,23 @@ static void early_superio_config_w83627ehg(void) pnp_exit_ext_func_mode(dev); }
-static void rcba_config(void) +void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + // Enable HWM at 0x290 + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); + + early_superio_config_w83627ehg(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -152,7 +152,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; }
-static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -206,56 +206,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; }
-#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - ich7_enable_lpc(); - early_superio_config_w83627ehg(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index f8fc155..1d0b5be 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -31,7 +31,6 @@ #include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -56,7 +55,7 @@ void setup_ich7_gpios(void) outl(0x000300fd, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ }
-static void ich7_enable_lpc(void) +void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -66,9 +65,12 @@ static void ich7_enable_lpc(void) pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d); // Enable SuperIO Power Management Events pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681); + /* Enable SuperIO PM */ + lpc47m15x_enable_serial(PME_DEV, 0x680); + lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ }
-static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -84,7 +86,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; }
-static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -138,57 +140,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; }
-#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0, boot_mode = 0; - - if (bist == 0) - enable_lapic(); - - ich7_enable_lpc(); - /* Enable SuperIO PM */ - lpc47m15x_enable_serial(PME_DEV, 0x680); - lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected.\n"); - boot_mode = 1; - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : boot_mode, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 2a3cfe2..123222a 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 select OVERRIDE_CLOCK_DISABLE + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET
config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index d25d0bc..abb8710 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -31,8 +31,6 @@ #include <pc80/mc146818rtc.h> #include "option_table.h" #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include <superio/winbond/w83627thg/w83627thg.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" @@ -56,28 +54,6 @@ void setup_ich7_gpios(void) outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ }
-static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); - // Enable HWM at 0xa00 - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); - // COM3 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); - // COM4 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); -} - /* TODO: superio code should really not be in mainboard */ static void pnp_enter_func_mode(device_t dev) { @@ -199,7 +175,31 @@ static void early_superio_config_w83627thg(void) pnp_exit_func_mode(dev); }
-static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); + // Enable HWM at 0xa00 + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); + + early_superio_config_w83627thg(); +} + +void rcba_config(void) { u32 reg32;
@@ -258,7 +258,7 @@ static void rcba_config(void) // RCBA32(0x341c) = 0x00000001; }
-static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -312,61 +312,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; }
-#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - early_superio_config_w83627thg(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index fbe2c72..0aa8204 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -22,6 +22,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET + config MAINBOARD_DIR string default lenovo/t60 diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 8baeea6..3a97c51 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -34,8 +34,6 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -74,8 +72,26 @@ void setup_ich7_gpios(void) outl(0x000300a3, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ }
-static void ich7_enable_lpc(void) +static void early_superio_config(void) { + int timeout = 100000; + device_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0xa0); + + while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void ich7_enable_lpc(void) +{ + int dock_err; + // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // decode range @@ -94,25 +110,26 @@ static void ich7_enable_lpc(void) /* range 0x1680 - 0x169f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); -}
-static void early_superio_config(void) -{ - int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0xa0); + /* We want early GPIO setup, to be able to detect legacy I/O module */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + /* Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + setup_ich7_gpios();
- while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) - udelay(1000); + dock_err = dlpc_init();
- /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { + dock_connect(); + early_superio_config(); + } }
-static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(0x0014) = 0x80000001; @@ -131,7 +148,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; }
-static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -185,87 +202,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; }
-#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - int dock_err; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; - - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - /* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); - setup_ich7_gpios(); - - dock_err = dlpc_init(); - - /* We prefer Legacy I/O module over docking */ - if (legacy_io_present()) { - legacy_io_init(); - early_superio_config(); - } else if (!dock_err && dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Setup the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x52); + read_spd(&spd[2], 0x51); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 0125d8c..ecbc9e8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select INTEL_EDID + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET
config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index fbfbd7c..881a42e 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -34,8 +34,6 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -81,7 +79,23 @@ void setup_ich7_gpios(void) outl(0x00030043, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ }
-static void ich7_enable_lpc(void) +static void early_superio_config(void) +{ + int timeout = 100000; + device_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0x06); + + while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); @@ -101,25 +115,19 @@ static void ich7_enable_lpc(void) /* range 0x1680 - 0x169f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); -} - -static void early_superio_config(void) -{ - int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0x06); - - while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) - udelay(1000);
- /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); + dlpc_init(); + /* dock_init initializes the DLPC switch on + * thinpad side, so this is required even + * if we're undocked. + */ + if (dock_present()) { + dock_connect(); + early_superio_config(); + } }
-static void rcba_config(void) +void rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(0x0014) = 0x80000001; @@ -138,7 +146,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; }
-static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -192,81 +200,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; }
-#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; - - - timestamp_init(get_initial_timestamp()); - timestamp_add_now(TS_START_ROMSTAGE); - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - - dlpc_init(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (dock_present()) { - dock_connect(); - early_superio_config(); - } - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - timestamp_add_now(TS_BEFORE_INITRAM); - sdram_initialize(s3resume ? 2 : 0, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); - - timestamp_add_now(TS_END_ROMSTAGE); - + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x52); + read_spd(&spd[2], 0x51); + read_spd(&spd[3], 0x53); } diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index efe75a3..e0c7a15 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -19,6 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION select INTEL_INT15 + select NORTHBRIDGE_INTEL_EARLY_PCI_RESET + select NORTHBRIDGE_INTEL_ARTEC_DONGLE
config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index c4bdcf4..ba56916 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -32,8 +32,6 @@ #include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include <cpu/x86/bist.h> -#include <halt.h> #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" @@ -68,27 +66,6 @@ void setup_ich7_gpios(void) // ------------------------------------------------------------ }
-static void ich7_enable_lpc(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT - } - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); - // Enable 0x02e0 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); - // COM3 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); - // COM4 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); -} - /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic @@ -148,7 +125,30 @@ static void early_superio_config(void) pnp_exit_ext_func_mode(dev); }
-static void rcba_config(void) +void ich7_enable_lpc(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) { + lpt_en = 1<<2; // enable LPT + } + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0007); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0b | lpt_en); + // Enable 0x02e0 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x02e1); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x001c); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00fc0601); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + + early_superio_config(); +} + +void rcba_config(void) { /* Set up virtual channel 0 */ //RCBA32(0x0014) = 0x80000001; @@ -173,7 +173,7 @@ static void rcba_config(void) RCBA32(0x1e98) = 0x000c0801; }
-static void early_ich7_init(void) +void early_ich7_init(void) { uint8_t reg8; uint32_t reg32; @@ -227,71 +227,10 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; }
-static void init_artec_dongle(void) -{ - // Enable 4MB decoding - outb(0xf1, 0x88); - outb(0xf4, 0x88); -} - -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_get_spd(spd_raw_data *spd) { - int s3resume = 0; - - if (bist == 0) - enable_lapic(); - - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - - ich7_enable_lpc(); - early_superio_config(); - - /* Set up the console */ - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); - outb(0x6, 0xcf9); - halt(); - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - /* This has to happen after i945_early_initialization() */ - init_artec_dongle(); - - s3resume = southbridge_detect_s3_resume(); - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(s3resume ? 2 : 0, NULL); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(s3resume); + read_spd(&spd[0], 0x50); + read_spd(&spd[1], 0x51); + read_spd(&spd[2], 0x52); + read_spd(&spd[3], 0x53); } diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index c578011..086be8a 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -36,6 +36,10 @@ config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n config NORTHBRIDGE_INTEL_SUBTYPE_I945GM def_bool n +config NORTHBRIDGE_INTEL_EARLY_PCI_RESET + def_bool n +config NORTHBRIDGE_INTEL_ARTEC_DONGLE + def_bool n
config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08977f2..b3730eb 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -26,6 +26,11 @@ #include <halt.h> #include <string.h> #include "i945.h" +#include <timestamp.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> +#include "raminit.h" +#include <halt.h>
int i945_silicon_revision(void) { @@ -980,3 +985,85 @@ void i945_late_initialization(int s3resume)
i945_prepare_resume(s3resume); } + + +static void init_artec_dongle(void) +{ + // Enable 4MB decoding + outb(0xf1, 0x88); + outb(0xf4, 0x88); +} + +void main(unsigned long bist) +{ + int s3resume = 0; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_EARLY_PCI_RESET)) { + /* Force PCIRST# */ + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + udelay(200 * 1000); + pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + } + + ich7_enable_lpc(); + + /* Set up the console */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, + "Soft reset detected, rebooting properly.\n"); + outb(0x6, 0xcf9); + halt(); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* This probably should be unconditional as artec dongle can + be used on any board but I have no hardware to test it. + */ + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_ARTEC_DONGLE)) { + /* This has to happen after i945_early_initialization() */ + init_artec_dongle(); + } + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + timestamp_add_now(TS_BEFORE_INITRAM); + sdram_initialize(s3resume ? 2 : 0); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); + + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e9b6e3f..187bcf5 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -51,18 +51,15 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21)
-static int get_dimm_spd_address(struct sys_info *sysinfo, int device) +void read_spd(spd_raw_data * spd, u8 addr) { - if (sysinfo->spd_addresses) - return sysinfo->spd_addresses[device]; - else - return DIMM0 + device; - -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); + int j; + int val; + val = smbus_read_byte(addr, 0); + if (val < 0) + return; + for (j = 1; j < 256; j++) + (*spd)[j] = smbus_read_byte(addr, j); }
static __attribute__((noinline)) void do_ram_command(u32 command) @@ -330,7 +327,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; + int dimmno;
/** * i945 supports two DIMMs, in two configurations: @@ -353,6 +350,9 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n"); }
+ memset(sysinfo->spd, 0, sizeof(sysinfo->spd)); + mainboard_get_spd(sysinfo->spd); + /** * Since we only support two DIMMs in total, there is a limited number * of combinations. This function returns the type of DIMMs. @@ -372,62 +372,61 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) * */
- for (i=0; i<(2 * DIMM_SOCKETS); i++) { - int device = get_dimm_spd_address(sysinfo, i); + for (dimmno=0; dimmno<(2 * DIMM_SOCKETS); dimmno++) { u8 reg8;
/* Initialize the socket information with a sane value */ - sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_NOT_POPULATED;
/* Dual Channel not supported, but Channel 1? Bail out */ - if (!sdram_capabilities_dual_channel() && (i >> 1)) + if (!sdram_capabilities_dual_channel() && (dimmno >> 1)) continue;
/* Two DIMMs per channel not supported, but odd DIMM number? */ - if (!sdram_capabilities_two_dimms_per_channel() && (i& 1)) + if (!sdram_capabilities_two_dimms_per_channel() && (dimmno& 1)) continue;
- printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (dimmno >> 1), (dimmno & 1));
- if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { + if (sysinfo->spd[dimmno][SPD_MEMORY_TYPE] != SPD_MEMORY_TYPE_SDRAM_DDR2) { printk(BIOS_DEBUG, "N/A\n"); continue; }
- reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); + reg8 = sysinfo->spd[dimmno][SPD_DIMM_CONFIG_TYPE]; if (reg8 == ERROR_SCHEME_ECC) die("Error: ECC memory not supported by this chipset\n");
- reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); + reg8 = sysinfo->spd[dimmno][SPD_MODULE_ATTRIBUTES]; if (reg8 & MODULE_BUFFERED) die("Error: Buffered memory not supported by this chipset\n"); if (reg8 & MODULE_REGISTERED) die("Error: Registered memory not supported by this chipset\n");
- switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) { + switch (sysinfo->spd[dimmno][SPD_PRIMARY_SDRAM_WIDTH]) { case 0x08: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { + switch (sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS] & 0x0f) { case 1: printk(BIOS_DEBUG, "x8DDS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X8DDS; break; case 0: printk(BIOS_DEBUG, "x8DS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X8DS; break; default: printk(BIOS_DEBUG, "Unsupported.\n"); } break; case 0x10: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { + switch (sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS] & 0x0f) { case 1: printk(BIOS_DEBUG, "x16DS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X16DS; break; case 0: printk(BIOS_DEBUG, "x16SS\n"); - sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; + sysinfo->dimm[dimmno] = SYSINFO_DIMM_X16SS; break; default: printk(BIOS_DEBUG, "Unsupported.\n"); @@ -437,7 +436,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) die("Unsupported DDR-II memory width.\n"); }
- dimm_mask |= (1 << i); + dimm_mask |= (1 << dimmno); }
if (!dimm_mask) { @@ -465,7 +464,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo) continue;
/* Is the current DIMM a stacked DIMM? */ - if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4)) + if (sysinfo->spd[i][SPD_NUM_DIMM_BANKS] & (1 << 4)) sysinfo->package = 1; } } @@ -482,8 +481,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
for (i=0; i<2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) - cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_ACCEPTABLE_CAS_LATENCIES); + cas_mask &= sysinfo->spd[i][SPD_ACCEPTABLE_CAS_LATENCIES]; }
if(!cas_mask) { @@ -495,7 +493,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask) { - int i, j, idx; + int dimmno, j, idx; int lowest_common_cas = 0; int max_ram_speed = 0;
@@ -536,16 +534,15 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 int freq_cas_mask = cas_mask;
PRINTK_DEBUG("Probing Speed %d\n", j); - for (i=0; i<2*DIMM_SOCKETS; i++) { - int device = get_dimm_spd_address(sysinfo, i); + for (dimmno=0; dimmno<2*DIMM_SOCKETS; dimmno++) { int current_cas_mask;
- PRINTK_DEBUG(" DIMM: %d\n", i); - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { + PRINTK_DEBUG(" DIMM: %d\n", dimmno); + if (sysinfo->dimm[dimmno] == SYSINFO_DIMM_NOT_POPULATED) { continue; }
- current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES); + current_cas_mask = sysinfo->spd[dimmno][SPD_ACCEPTABLE_CAS_LATENCIES];
while (current_cas_mask) { int highest_supported_cas = 0, current_cas = 0; @@ -571,11 +568,11 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
idx = highest_supported_cas - current_cas; PRINTK_DEBUG("idx=%d, ", idx); - PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx])); - PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1])); + PRINTK_DEBUG("tCLK=%x, ", sysinfo->spd[dimmno][spd_lookup_table[2*idx]]); + PRINTK_DEBUG("tAC=%x", sysinfo->spd[dimmno][spd_lookup_table[(2*idx)+1]]);
- if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && - spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { + if (sysinfo->spd[dimmno][spd_lookup_table[2*idx]] <= ddr2_speeds_table[2*j] && + sysinfo->spd[dimmno][spd_lookup_table[(2*idx)+1]] <= ddr2_speeds_table[(2*j)+1]) { PRINTK_DEBUG(": OK\n"); break; } @@ -587,7 +584,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
freq_cas_mask &= current_cas_mask; if (!current_cas_mask) { - PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i); + PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", dimmno); break; } } @@ -639,7 +636,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue;
- reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + reg8 = sysinfo->spd[i][SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY]; if (!reg8) { die("Invalid tRAS value.\n"); } @@ -679,7 +676,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue;
- reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME); + reg8 = sysinfo->spd[i][SPD_MIN_ROW_PRECHARGE_TIME]; if (!reg8) { die("Invalid tRP value.\n"); } @@ -720,7 +717,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue;
- reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY); + reg8 = sysinfo->spd[i][SPD_MIN_RAS_TO_CAS_DELAY]; if (!reg8) { die("Invalid tRCD value.\n"); } @@ -760,7 +757,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue;
- reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME); + reg8 = sysinfo->spd[i][SPD_WRITE_RECOVERY_TIME]; if (!reg8) { die("Invalid tWR value.\n"); } @@ -841,8 +838,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue;
- refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_REFRESH) & ~(1 << 7); + refresh = sysinfo->spd[i][SPD_REFRESH] & ~(1 << 7);
/* 15.6us */ if (!refresh) @@ -870,8 +866,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue;
- if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + if (!(sysinfo->spd[i][SPD_SUPPORTED_BURST_LENGTHS] & SPD_BURST_LENGTH_8)) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -1407,41 +1402,40 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, rows, columns, device; + int value, low, rows, columns;
- device = get_dimm_spd_address(sysinfo, dimmno); sz.side1 = 0; sz.side2 = 0;
- rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + rows = sysinfo->spd[dimmno][SPD_NUM_ROWS]; /* rows */ if (rows < 0) goto hw_err; if ((rows & 0xf) == 0) goto val_err; sz.side1 += rows & 0xf;
- columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + columns = sysinfo->spd[dimmno][SPD_NUM_COLUMNS]; /* columns */ if (columns < 0) goto hw_err; if ((columns & 0xf) == 0) goto val_err; sz.side1 += columns & 0xf;
- value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */ + value = sysinfo->spd[dimmno][SPD_NUM_BANKS_PER_SDRAM]; /* banks */ if (value < 0) goto hw_err; if ((value & 0xff) == 0) goto val_err; sz.side1 += log2(value & 0xff);
/* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */ + value = sysinfo->spd[dimmno][SPD_MODULE_DATA_WIDTH_MSB]; /* (high byte) */ if (value < 0) goto hw_err; value &= 0xff; value <<= 8;
- low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */ + low = sysinfo->spd[dimmno][SPD_MODULE_DATA_WIDTH_LSB]; /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); if ((value != 72) && (value != 64)) goto val_err; sz.side1 += log2(value);
/* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */ + value = sysinfo->spd[dimmno][SPD_NUM_DIMM_BANKS]; /* number of physical banks */
if (value < 0) goto hw_err; value &= 7; @@ -1494,8 +1488,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
sz = sdram_get_dimm_size(sysinfo, i);
- sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_NUM_BANKS_PER_SDRAM); /* banks */ + sysinfo->banks[i] = sysinfo->spd[i][SPD_NUM_BANKS_PER_SDRAM]; /* banks */
if (sz.side1 < 30) die("DDR-II rank size smaller than 128MB is not supported.\n"); @@ -1575,24 +1568,21 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
static int sdram_set_row_attributes(struct sys_info *sysinfo) { - int i, value; + int dimmno, value; u16 dra0=0, dra1=0, dra = 0;
printk(BIOS_DEBUG, "Setting row attributes... \n"); - for(i=0; i < 2 * DIMM_SOCKETS; i++) { - u16 device; + for(dimmno=0; dimmno < 2 * DIMM_SOCKETS; dimmno++) { u8 columnsrows;
- if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { + if (sysinfo->dimm[dimmno] == SYSINFO_DIMM_NOT_POPULATED) { continue; }
- device = get_dimm_spd_address(sysinfo, i); - - value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + value = sysinfo->spd[dimmno][SPD_NUM_ROWS]; /* rows */ columnsrows = (value & 0x0f);
- value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + value = sysinfo->spd[dimmno][SPD_NUM_COLUMNS]; /* columns */ columnsrows |= (value & 0xf) << 4;
switch (columnsrows) { @@ -1605,14 +1595,14 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo) }
/* Double Sided DIMMs? */ - if (sysinfo->banksize[(2 * i) + 1] != 0) { + if (sysinfo->banksize[(2 * dimmno) + 1] != 0) { dra = (dra << 4) | dra; }
- if (i < DIMM_SOCKETS) - dra0 |= (dra << (i*8)); + if (dimmno < DIMM_SOCKETS) + dra0 |= (dra << (dimmno*8)); else - dra1 |= (dra << ((i - DIMM_SOCKETS)*8)); + dra1 |= (dra << ((dimmno - DIMM_SOCKETS)*8)); }
MCHBAR16(C0DRA0) = dra0; @@ -3050,7 +3040,7 @@ static void sdram_setup_processor_side(void) /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 */ -void sdram_initialize(int boot_path, const u8 *spd_addresses) +void sdram_initialize(int boot_path) { struct sys_info sysinfo; u8 reg8, cas_mask; @@ -3060,7 +3050,6 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) memset(&sysinfo, 0, sizeof(sysinfo));
sysinfo.boot_path = boot_path; - sysinfo.spd_addresses = spd_addresses;
/* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */ sdram_get_dram_configuration(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 9eb4193..20fbe8c 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -20,6 +20,8 @@ #ifndef RAMINIT_H #define RAMINIT_H
+#include <device/dram/ddr3.h> + #define DIMM_SOCKETS 2
#define DIMM_TCO_BASE 0x30 @@ -63,14 +65,18 @@ struct sys_info { u8 banks[2 * DIMM_SOCKETS];
u8 banksize[2 * 2 * DIMM_SOCKETS]; - const u8 *spd_addresses; - + spd_raw_data spd[4]; } __attribute__ ((packed));
void receive_enable_adjust(struct sys_info *sysinfo); -void sdram_initialize(int boot_path, const u8 *sdram_addresses); +void sdram_initialize(int boot_path); int fixup_i945_errata(void); void udelay(u32 us); +void mainboard_get_spd(spd_raw_data *spd); +void read_spd(spd_raw_data *spd, u8 addr); +void ich7_enable_lpc(void); +void rcba_config(void); +void early_ich7_init(void);
#if CONFIG_DEBUG_RAM_SETUP void sdram_dump_mchbar_registers(void);