Attention is currently required from: Arthur Heymans.
3 comments:
File src/drivers/amd/agesa/s3_mtrr.c:
Patch Set #4, Line 67: disable_cache();
Disappears without argumentation.
Patch Set #4, Line 47: mtrr_save->mtrr_phys_mask[i] = rdmsr(MTRR_PHYS_BASE(i));
MTRR_PHYS_MASK(i)
Maybe you want to read BASE() first, althought it does not matter
Patch Set #4, Line 82: wrmsr(MTRR_PHYS_BASE(i), mtrr_save->mtrr_phys_mask[i]);
MTRR_PHYS_MASK(i)
Since valid bit is in MASK register, BASE should be programmed first.
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