Patrick Georgi submitted this change.
soc/mediatek/mt8183: Fix programming error of DRAMC setting
1. The ac timing of 2400Mbps should use diff params with 1600Mbps.
2. Fix the typo error of save shuffle function for DVFS.
BRANCH=kukui
BUG=none
TEST=emerge-kukui coreboot
Change-Id: I5edac32938def50836f386426e7deb652b80d42d
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
---
M src/soc/mediatek/mt8183/emi.c
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index cf104f8..07d1cc8 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -325,7 +325,7 @@
{
struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = {
[LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62},
- [LP4X_DDR2400] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62},
+ [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .tx_ref_cnt = 91},
[LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119},
[LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138},
};
@@ -456,9 +456,9 @@
value = read32(src_addr) & 0x7f;
if (dst_shuffle == DRAM_DFS_SHUFFLE_2)
- clrsetbits32(dst_addr, 0x7f << 0x8, value << 0x8);
+ clrsetbits32(dst_addr, 0x7f << 8, value << 8);
else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
- clrsetbits32(dst_addr, 0x7f << 0x16, value << 0x16);
+ clrsetbits32(dst_addr, 0x7f << 16, value << 16);
/* DRAMC-exception-2 */
src_addr = (u8 *)&ch[chn].ao.dvfsdll;
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