5 comments:
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
This change will remove, I used for verify buildbot:)
Ack.
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
unrelated change
File src/soc/intel/alderlake/chip.h:
Patch Set #14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
I kept this for special assigning :
Ah, I had missed that adlrvp is already using the PEG port clock mapping as well. We need to enable another config structure for the CPU PCIe ports. The above config can be renamed to pch_pcie_rp and create a similar one for cpu_pcie_rp:
struct pcie_rp_config {
uint8_t clk_src;
uint8_t clk_req;
uint32_t flags;
};
struct pcie_rp_config pch_pcie_rp[MAX_PCH_PCIE_ROOT_PORTS];
struct pcie_rp_config cpu_pcie_rp[MAX_CPU_PCIE_ROOT_PORTS];
SoC code will have to handle both these structures:
enum {
PCH_PCIE_RP,
CPU_PCIE_RP,
};
static uint8_t pcie_clk_src_usage(enum pcie_rp_type type, const struct pcie_rp_config *cfg, int rp_number)
{
if (pcie_is_flag_enabled(cfg, PCIE_RP_ALWAYS_ON_CLK))
return 0x80;
if (type == PCH_PCIE_RP)
return rp_number;
if (type == CPU_PCIE_RP)
return 0x40 + rp_number;
die ("Unsupported type!");
}
static uint32_t pcie_rp_init(enum pcie_rp_type type, const struct pcie_rp_config *cfg, size_t cfg_count)
{
mask = 0;
for (i = 0; i < cfg_count; i++, cfg++) {
if (!pcie_is_flag_enabled(cfg, PCIE_RP_ENABLED))
continue;
mask |= (1 << i);
if (!pcie_is_flag_enabled(cfg, PCIE_RP_CLK_NOTUSED))
continue;
m_cfg->PcieClkSrcClkReq[cfg->clk_src] = cfg->clk_req;
m_cfg->PcieClkSrcUsage[cfg->clk_src] = pcie_clk_src_usage(type, cfg, i);
}
return mask;
}
m_cfg->PcieRpEnableMask = pcie_rp_init(PCH_PCIE_RP, config->pch_pcie_rp, ARRAY_SIZE(config->pch_pcie_rp));
m_cfg->CpuPcieRpEnableMask = pcie_rp_init(CPU_PCIE_RP, config->cpu_pcie_rp, ARRAY_SIZE(config->cpu_pcie_rp));
File src/soc/intel/alderlake/romstage/fsp_params.c:
memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
sizeof(config->PcieClkSrcUsage));
Need to copy the special usage.
See comment on chip.h.
m_cfg->PcieClkSrcClkReq[config->pcie_rp[i].clk_req] =
config->pcie_rp[i].clk_src;
Take Brya for example. […]
No, it is the other way around:
PcieClkSrcClkReq[4] = 3;
PcieClkSrcUsage[4] = 7;
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