Lijian Zhao has uploaded this change for review.
soc/intel/cannonlake: Enable options for wakeup
Cannonlake FSP silicon init have dedicated wake up capability settings
for several IP, expose the selection into coreboot.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I260e655417ca79d458784c9ec0e8e35d03b02e06
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30447/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3a723d2..e5a3ae1 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -302,6 +302,13 @@
/* SATA Power Optimizer */
uint8_t satapwroptimize;
+
+ /* Wake Up Capability */
+ uint8_t codec_wake_sx;
+ uint8_t pcie_wake_deepsx;
+ uint8_t wlan_wake_sx;
+ uint8_t wlan_wake_deepsx;
+ uint8_t glan_wake_deepsx;
};
typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 78b27e9..9a24242 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -225,6 +225,14 @@
/* Power Optimizer */
params->PchPwrOptEnable = config->dmipwroptimize;
params->SataPwrOptEnable = config->satapwroptimize;
+
+ /* Wakeup Capability */
+ params->PchHdaCodecSxWakeCapability = config->codec_wake_sx;
+ params->PchPmWoWlanEnable = config->wlan_wake_sx;
+ params->PchPmPcieWakeFromDeepSx = config->pcie_wake_deepsx;
+ params->PchPmWoWlanDeepSxEnable = config->wlan_wake_deepsx;
+ params->PchPmLanWakeFromDeepSx = config->glan_wake_deepsx;
+
}
/* Mainboard GPIO Configuration */
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