Felix Singer has uploaded this change for review.

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soc/intel/cnl: PEG devices

Change-Id: Ie2dd90edf10f1cefed26fe577508a9c8af3eb532
Signed-off-by: Felix Singer <felix.singer@secunet.com>
---
M src/soc/intel/cannonlake/include/soc/pci_devs.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/44741/1

diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index b0430e4..35f0e59 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -22,6 +22,16 @@
 #define  SA_DEV_ROOT		PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
 #endif
 
+#define SA_DEV_SLOT_PEG		0x01
+#define  SA_DEVFN_PEG0		PCI_DEVFN(SA_DEV_SLOT_PEG, 0)
+#define  SA_DEVFN_PEG1		PCI_DEVFN(SA_DEV_SLOT_PEG, 1)
+#define  SA_DEVFN_PEG2		PCI_DEVFN(SA_DEV_SLOT_PEG, 2)
+#define  SA_DEVFN_PEG3		PCI_DEVFN(SA_DEV_SLOT_PEG, 3)
+#define  SA_DEV_PEG0		PCI_DEV(0, SA_DEV_SLOT_PEG, 0)
+#define  SA_DEV_PEG1		PCI_DEV(0, SA_DEV_SLOT_PEG, 1)
+#define  SA_DEV_PEG2		PCI_DEV(0, SA_DEV_SLOT_PEG, 2)
+#define  SA_DEV_PEG3		PCI_DEV(0, SA_DEV_SLOT_PEG, 3)
+
 #define SA_DEV_SLOT_IGD		0x02
 #define  SA_DEVFN_IGD		PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
 #define  SA_DEV_IGD		PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index ac42e00..4b2ad50 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -131,6 +131,20 @@
 	if (config->DisableHeciRetry)
 		tconfig->DisableHeciRetry = config->DisableHeciRetry;
 #endif
+
+#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
+	dev = pcidev_path_on_root(SA_DEVFN_PEG0);
+	m_cfg->Peg0Enable = is_dev_enabled(dev);
+
+	dev = pcidev_path_on_root(SA_DEVFN_PEG1);
+	m_cfg->Peg1Enable = is_dev_enabled(dev);
+
+	dev = pcidev_path_on_root(SA_DEVFN_PEG2);
+	m_cfg->Peg2Enable = is_dev_enabled(dev);
+
+	dev = pcidev_path_on_root(SA_DEVFN_PEG3);
+	m_cfg->Peg3Enable = is_dev_enabled(dev);
+#endif
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

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