Felix Held submitted this change.
sb/intel: Use `bool` for PCIe coalescing option
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/apple/macbookair4_2/devicetree.cb
M src/mainboard/asrock/b75pro3-m/devicetree.cb
M src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
M src/mainboard/compulab/intense_pc/devicetree.cb
M src/mainboard/dell/optiplex_9010/devicetree.cb
M src/mainboard/google/auron/variants/buddy/overridetree.cb
M src/mainboard/google/auron/variants/samus/overridetree.cb
M src/mainboard/google/beltino/devicetree.cb
M src/mainboard/google/butterfly/devicetree.cb
M src/mainboard/google/jecht/devicetree.cb
M src/mainboard/google/link/devicetree.cb
M src/mainboard/google/parrot/devicetree.cb
M src/mainboard/google/stout/devicetree.cb
M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
M src/mainboard/hp/snb_ivb_laptops/devicetree.cb
M src/mainboard/hp/z220_sff_workstation/devicetree.cb
M src/mainboard/kontron/ktqm77/devicetree.cb
M src/mainboard/lenovo/l520/devicetree.cb
M src/mainboard/lenovo/s230u/devicetree.cb
M src/mainboard/lenovo/t420/devicetree.cb
M src/mainboard/lenovo/t420s/devicetree.cb
M src/mainboard/lenovo/t430/devicetree.cb
M src/mainboard/lenovo/t430s/devicetree.cb
M src/mainboard/lenovo/t520/devicetree.cb
M src/mainboard/lenovo/t530/devicetree.cb
M src/mainboard/lenovo/x131e/devicetree.cb
M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
M src/mainboard/lenovo/x220/devicetree.cb
M src/mainboard/lenovo/x230/devicetree.cb
M src/mainboard/msi/ms7707/devicetree.cb
M src/mainboard/roda/rv11/variants/rv11/devicetree.cb
M src/mainboard/roda/rv11/variants/rw11/devicetree.cb
M src/mainboard/sapphire/pureplatinumh61/devicetree.cb
M src/mainboard/supermicro/x9scl/devicetree.cb
M src/soc/intel/broadwell/pch/chip.h
M src/soc/intel/broadwell/pch/pcie.c
M src/southbridge/intel/bd82x6x/chip.h
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/i82801gx/chip.h
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/lynxpoint/chip.h
M src/southbridge/intel/lynxpoint/pcie.c
42 files changed, 50 insertions(+), 49 deletions(-)
diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb
index 8f7573a..6ea033e 100644
--- a/src/mainboard/apple/macbookair4_2/devicetree.cb
+++ b/src/mainboard/apple/macbookair4_2/devicetree.cb
@@ -32,7 +32,7 @@
register "gen4_dec" = "0x00fc0701"
register "gpi7_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x1"
device pci 16.0 on # Management Engine Interface 1
diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb
index 93d37dc..0f7d0a8 100644
--- a/src/mainboard/asrock/b75pro3-m/devicetree.cb
+++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb
@@ -38,7 +38,7 @@
register "gen2_dec" = "0x000c0241"
register "gen3_dec" = "0x000c0251"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
- register "pcie_port_coalesce" = "0"
+ register "pcie_port_coalesce" = "false"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3f"
register "superspeed_capable_ports" = "0x0000000f"
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
index 9dcf2b7..0162547 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb
@@ -6,7 +6,7 @@
chip southbridge/intel/bd82x6x
register "gen1_dec" = "0x000c0291"
register "gen4_dec" = "0x0000ff29"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 1c.0 on end # PCIe Port 1 PCIEX_16_3
device pci 1c.1 on end # PCIe Port 2 RTL8111F
diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb
index b3b1a1c..6979615 100644
--- a/src/mainboard/compulab/intense_pc/devicetree.cb
+++ b/src/mainboard/compulab/intense_pc/devicetree.cb
@@ -37,7 +37,7 @@
register "gen3_dec" = "0x000406f1"
register "gen4_dec" = "0x000c06a1"
register "gpi7_routing" = "2"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
# Intense PC SATA portmap:
# Port 0: internal 2.5" bay
diff --git a/src/mainboard/dell/optiplex_9010/devicetree.cb b/src/mainboard/dell/optiplex_9010/devicetree.cb
index fd95081..ef0a0e3 100644
--- a/src/mainboard/dell/optiplex_9010/devicetree.cb
+++ b/src/mainboard/dell/optiplex_9010/devicetree.cb
@@ -28,7 +28,7 @@
register "gen2_dec" = "0x007c0901"
register "gen3_dec" = "0x003c07e1"
register "gen4_dec" = "0x001c0901"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x7"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index 0570cdc..ad8e50c 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -33,7 +33,7 @@
register "pcie_port_force_aspm" = "0x10"
# Enable port coalescing
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index 0a92efe..cfb4812 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -36,7 +36,7 @@
# Force enable ASPM for PCIe Port 3
register "pcie_port_force_aspm" = "0x04"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013b0000"
diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb
index 8c54f6a..8eada25 100644
--- a/src/mainboard/google/beltino/devicetree.cb
+++ b/src/mainboard/google/beltino/devicetree.cb
@@ -44,7 +44,7 @@
register "pcie_port_force_aspm" = "0x10"
# Enable port coalescing
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 725cbd1..c79526e 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -58,7 +58,7 @@
register "gen2_dec" = "0x00040381"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index 08b2c95..e972baa 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -38,7 +38,7 @@
register "pcie_port_force_aspm" = "0x10"
# Enable port coalescing
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index fda74da..49c3476 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -56,7 +56,7 @@
register "gen2_dec" = "0x00fc0901"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index d748277..6850cf2 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -54,7 +54,7 @@
register "gen2_dec" = "0x00040069"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index ad700ce..b38adaf 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -61,7 +61,7 @@
register "gen3_dec" = "0x0001C1611"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
index 76d04d6..98e48ef 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
+++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
@@ -28,7 +28,7 @@
register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0801"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0xf"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb
index 3dd8825..2bfbacd 100644
--- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb
+++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb
@@ -29,7 +29,7 @@
device pci 00.0 on end # Host bridge
chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0"
diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb
index 5204e60..0de9cfa 100644
--- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb
+++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb
@@ -28,7 +28,7 @@
register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0801"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0xf"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb
index a878019..31bee5d 100644
--- a/src/mainboard/kontron/ktqm77/devicetree.cb
+++ b/src/mainboard/kontron/ktqm77/devicetree.cb
@@ -32,7 +32,7 @@
#register "gen4_dec" = "0x00000000"
# Disable root port coalescing
- register "pcie_port_coalesce" = "0"
+ register "pcie_port_coalesce" = "false"
register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f"
diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb
index 86205f8..6c2dabe 100644
--- a/src/mainboard/lenovo/l520/devicetree.cb
+++ b/src/mainboard/lenovo/l520/devicetree.cb
@@ -38,7 +38,7 @@
register "gpi13_routing" = "2"
register "gpi6_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3b"
diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb
index 3c1fc9e..14d849d 100644
--- a/src/mainboard/lenovo/s230u/devicetree.cb
+++ b/src/mainboard/lenovo/s230u/devicetree.cb
@@ -36,7 +36,7 @@
register "gpi13_routing" = "2"
register "gpi7_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x5"
register "superspeed_capable_ports" = "0x0000000f"
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index 457ccbe..c934f5f 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -55,7 +55,7 @@
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# device specific SPI configuration
register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 32736a8..1d6adaf 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -57,7 +57,7 @@
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
# device specific SPI configuration
register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 112dfe7..141faa9 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -35,7 +35,7 @@
register "gpi13_routing" = "2"
register "gpi1_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x17"
register "superspeed_capable_ports" = "0x0000000f"
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index 75a65f9..942f029 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -58,7 +58,7 @@
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "docking_supported" = "1"
register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index a1e24d5..9c75231 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -55,7 +55,7 @@
register "gen4_dec" = "0x0c06a1"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index ffa0b93..5cfa207 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -52,7 +52,7 @@
register "gen4_dec" = "0x0c06a1"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb
index abe40b1..ee8a2e0 100644
--- a/src/mainboard/lenovo/x131e/devicetree.cb
+++ b/src/mainboard/lenovo/x131e/devicetree.cb
@@ -55,7 +55,7 @@
register "xhci_overcurrent_mapping" = "0x00000c03"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
index 30260b0..cbf1141 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
@@ -57,7 +57,7 @@
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index b239d64..923c88b 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -55,7 +55,7 @@
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 1f81311..30a7916 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -58,7 +58,7 @@
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb
index 6c97e1f..8e5df58 100644
--- a/src/mainboard/msi/ms7707/devicetree.cb
+++ b/src/mainboard/msi/ms7707/devicetree.cb
@@ -19,7 +19,7 @@
register "docking_supported" = "0"
register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0a01"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
index 8ba2697..6cb77e3 100644
--- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
@@ -46,7 +46,7 @@
register "gpe0_en" = "0x00800040"
# Disable root port coalescing
- register "pcie_port_coalesce" = "0"
+ register "pcie_port_coalesce" = "false"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
index 7e5555b..2291f61 100644
--- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
@@ -51,7 +51,7 @@
register "gpe0_en" = "0x00800040"
# Disable root port coalescing
- register "pcie_port_coalesce" = "0"
+ register "pcie_port_coalesce" = "false"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
index 876f920..d5f6fda 100644
--- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -14,7 +14,7 @@
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0a01"
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi.opprefixes" = "{ 0x50, 0x06 }"
diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb
index 49fcff5..284d8f3 100644
--- a/src/mainboard/supermicro/x9scl/devicetree.cb
+++ b/src/mainboard/supermicro/x9scl/devicetree.cb
@@ -20,7 +20,7 @@
register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff)
register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3)
register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff)
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x3f"
register "spi_lvscc" = "0x2005"
diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h
index 2164a31..84ad8fe 100644
--- a/src/soc/intel/broadwell/pch/chip.h
+++ b/src/soc/intel/broadwell/pch/chip.h
@@ -3,7 +3,7 @@
#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_
#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_
-#include <stdint.h>
+#include <types.h>
struct soc_intel_broadwell_pch_config {
/* GPE configuration */
@@ -47,7 +47,7 @@
uint32_t gen4_dec;
/* Enable linear PCIe Root Port function numbers starting at zero */
- uint8_t pcie_port_coalesce;
+ bool pcie_port_coalesce;
/* Force root port ASPM configuration with port bitmap */
uint8_t pcie_port_force_aspm;
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c
index 29915d6..5997768 100644
--- a/src/soc/intel/broadwell/pch/pcie.c
+++ b/src/soc/intel/broadwell/pch/pcie.c
@@ -2,6 +2,7 @@
#include <console/console.h>
#include <cpu/intel/haswell/haswell.h>
+#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pciexp.h>
@@ -15,7 +16,7 @@
#include <soc/intel/broadwell/pch/chip.h>
#include <southbridge/intel/lynxpoint/iobp.h>
#include <southbridge/intel/lynxpoint/lp_gpio.h>
-#include <delay.h>
+#include <types.h>
/* Low Power variant has 6 root ports. */
#define MAX_NUM_ROOT_PORTS 6
@@ -31,7 +32,7 @@
u32 b0d28f0_32c;
u32 b0d28f4_32c;
u32 b0d28f5_32c;
- int coalesce;
+ bool coalesce;
int gbe_port;
int num_ports;
struct device *ports[MAX_NUM_ROOT_PORTS];
@@ -274,7 +275,7 @@
/* If the first root port is disabled the coalesce ports. */
if (!rpc.ports[0]->enabled)
- rpc.coalesce = 1;
+ rpc.coalesce = true;
/* Perform clock gating configuration. */
pcie_enable_clock_gating();
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 797c93f..30c2675 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -4,7 +4,7 @@
#define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
#include <southbridge/intel/common/spi.h>
-#include <stdint.h>
+#include <types.h>
struct southbridge_intel_bd82x6x_config {
/**
@@ -58,7 +58,7 @@
uint32_t gen4_dec;
/* Enable linear PCIe Root Port function numbers starting at zero */
- uint8_t pcie_port_coalesce;
+ bool pcie_port_coalesce;
/* Override PCIe ASPM */
uint8_t pcie_aspm[8];
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 82b95f6..d24604c 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -319,7 +319,7 @@
* or the other devices will not be enumerated by the OS.
*/
if (!dev->enabled)
- config->pcie_port_coalesce = 1;
+ config->pcie_port_coalesce = true;
if (config->pcie_port_coalesce)
printk(BIOS_INFO,
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index 303536f..09a7126 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -3,7 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
#define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H
-#include <stdint.h>
+#include <types.h>
enum sata_mode {
SATA_MODE_AHCI = 0,
@@ -61,7 +61,7 @@
uint32_t sata_ports_implemented;
/* Enable linear PCIe Root Port function numbers starting at zero */
- uint8_t pcie_port_coalesce;
+ bool pcie_port_coalesce;
int c4onc3_enable:1;
int docking_supported:1;
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 8650673..b8918e8 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -137,7 +137,7 @@
static void root_port_commit_config(struct device *dev)
{
int i;
- int coalesce = 0;
+ bool coalesce = false;
if (dev->chip_info != NULL) {
const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
@@ -145,7 +145,7 @@
}
if (!rpc.ports[0]->enabled)
- coalesce = 1;
+ coalesce = true;
for (i = 0; i < rpc.num_ports; i++) {
struct device *pcie_dev;
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index 89bbb1c..12bb401 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -65,7 +65,7 @@
uint32_t gen4_dec;
/* Enable linear PCIe Root Port function numbers starting at zero */
- uint8_t pcie_port_coalesce;
+ bool pcie_port_coalesce;
/* Force root port ASPM configuration with port bitmap */
uint8_t pcie_port_force_aspm;
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 5f21e61..30773e6 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -28,7 +28,7 @@
u32 b0d28f0_32c;
u32 b0d28f4_32c;
u32 b0d28f5_32c;
- int coalesce;
+ bool coalesce;
int gbe_port;
int num_ports;
struct device *ports[MAX_NUM_ROOT_PORTS];
@@ -304,7 +304,7 @@
/* If the first root port is disabled the coalesce ports. */
if (!is_rp_enabled(1))
- rpc.coalesce = 1;
+ rpc.coalesce = true;
/* Perform clock gating configuration. */
pcie_enable_clock_gating();
To view, visit change 60416. To unsubscribe, or for help writing mail filters, visit settings.