Keith Hui has uploaded this change for review.

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sb/intel/i82371eb: Add support for reconfiguring GPO22/23

XOE# and XDIR# can be used as GPOs 23/22 if X-Bus functionality is not
required. Turns out asus/p2b-ls is using them to control termination
for the onboard SCSI buses. Add support to allow this reconfiguration.

Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9
Signed-off-by: Keith Hui <buurin@gmail.com>
---
M src/mainboard/asus/p2b-ls/devicetree.cb
M src/southbridge/intel/i82371eb/chip.h
M src/southbridge/intel/i82371eb/isa.c
3 files changed, 15 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38352/1

diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b-ls/devicetree.cb
index a9901b4..5e55278 100644
--- a/src/mainboard/asus/p2b-ls/devicetree.cb
+++ b/src/mainboard/asus/p2b-ls/devicetree.cb
@@ -8,6 +8,10 @@
     device pci 0.0 on end		# Host bridge
     device pci 1.0 on end		# PCI/AGP bridge
     chip southbridge/intel/i82371eb	# Southbridge
+      register "gpo" = "0x7fbfb9ff"
+      register "gpo22_enable" = "1"
+      register "lid_polarity" = "1"
+      register "thrm_polarity" = "1"
       device pci 4.0 on			# ISA bridge
         chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
           device pnp 3f0.0 on		# Floppy
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 28975a2..5b23ab1 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -28,6 +28,10 @@
 	int ide1_drive1_udma33_enable:1;
 	int ide_legacy_enable:1;
 	int usb_enable:1;
+	int gpo22_enable:1; /* GPO22/GPO23 (1) vs. XDIR#/XOE# (0) */
+	int gpo22:1;
+	int gpo23:1;
+	int pad:5;
 	/* acpi */
 	u32 gpo; /* gpio output default */
 	u8 lid_polarity;
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index bb88f7d..fd63440 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -28,6 +28,7 @@
 #include <arch/acpigen.h>
 #endif
 #include "i82371eb.h"
+#include "chip.h"
 
 #if CONFIG(IOAPIC)
 static void enable_intel_82093aa_ioapic(void)
@@ -63,6 +64,7 @@
 static void isa_init(struct device *dev)
 {
 	u32 reg32;
+	struct southbridge_intel_i82371eb_config *sb = dev->chip_info;
 
 	/* Initialize the real time clock (RTC). */
 	cmos_init(0);
@@ -77,9 +79,13 @@
 	/*
 	 * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
 	 * bus, which is a subset of ISA. We select the full ISA bus here.
+	 * Some boards use GPO22/23. That will be taken care of as well.
 	 */
 	reg32 = pci_read_config32(dev, GENCFG);
-	reg32 |= ISA;	/* Select ISA, not EIO. */
+
+	reg32 |= ISA |	/* Select ISA, not EIO. */
+		(sb->gpo22_enable << 28); /* Select GPO22/23 if configured. */
+
 	pci_write_config16(dev, GENCFG, reg32);
 
 	/* Initialize ISA DMA. */

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