Subrata Banik has uploaded this change for review.
device/pci_ids: Add new Intel PTL device IDs for PCIe
This patch adds new PCIe Root Port PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the PCIe driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I5913c6ac0a4766c14f23954be1e885d45f69d36a
Signed-off-by: Subrata Banik <subratabanik@google.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/pcie/pcie.c
2 files changed, 44 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83507/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 7261dbd..c4fa842 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3602,15 +3602,28 @@
#define PCI_DID_INTEL_LNL_PCIE_RP6 0xa83d
#define PCI_DID_INTEL_LNL_PCIE_RP7 0xa83e
#define PCI_DID_INTEL_LNL_PCIE_RP8 0xa83f
-#define PCI_DID_INTEL_PTL_PCIE_RP1 0xe438
-#define PCI_DID_INTEL_PTL_PCIE_RP2 0xe439
-#define PCI_DID_INTEL_PTL_PCIE_RP3 0xe43a
-#define PCI_DID_INTEL_PTL_PCIE_RP4 0xe43b
-#define PCI_DID_INTEL_PTL_PCIE_RP5 0xe43c
-#define PCI_DID_INTEL_PTL_PCIE_RP6 0xe43d
-#define PCI_DID_INTEL_PTL_PCIE_RP7 0xe43e
-#define PCI_DID_INTEL_PTL_PCIE_RP8 0xe43f
-
+#define PCI_DID_INTEL_PTL_H_PCIE_RP1 0xe438
+#define PCI_DID_INTEL_PTL_H_PCIE_RP2 0xe439
+#define PCI_DID_INTEL_PTL_H_PCIE_RP3 0xe43a
+#define PCI_DID_INTEL_PTL_H_PCIE_RP4 0xe43b
+#define PCI_DID_INTEL_PTL_H_PCIE_RP5 0xe43c
+#define PCI_DID_INTEL_PTL_H_PCIE_RP6 0xe43d
+#define PCI_DID_INTEL_PTL_H_PCIE_RP7 0xe43e
+#define PCI_DID_INTEL_PTL_H_PCIE_RP8 0xe43f
+#define PCI_DID_INTEL_PTL_H_PCIE_RP9 0xe461
+#define PCI_DID_INTEL_PTL_H_PCIE_RP10 0xe45c
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP1 0xe338
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP2 0xe339
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP3 0xe33a
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP4 0xe33b
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP5 0xe33c
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP6 0xe33d
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP7 0xe33e
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP8 0xe33f
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP9 0xe361
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP10 0xe35c
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP11 0xe365
+#define PCI_DID_INTEL_PTL_U_H_PCIE_RP12 0xe366
#define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38
#define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39
#define PCI_DID_INTEL_RPP_S_PCIE_RP3 0x7a3a
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c
index 3c5e26a..ddea3b6 100644
--- a/src/soc/intel/common/block/pcie/pcie.c
+++ b/src/soc/intel/common/block/pcie/pcie.c
@@ -67,14 +67,28 @@
};
static const unsigned short pcie_device_ids[] = {
- PCI_DID_INTEL_PTL_PCIE_RP1,
- PCI_DID_INTEL_PTL_PCIE_RP2,
- PCI_DID_INTEL_PTL_PCIE_RP3,
- PCI_DID_INTEL_PTL_PCIE_RP4,
- PCI_DID_INTEL_PTL_PCIE_RP5,
- PCI_DID_INTEL_PTL_PCIE_RP6,
- PCI_DID_INTEL_PTL_PCIE_RP7,
- PCI_DID_INTEL_PTL_PCIE_RP8,
+ PCI_DID_INTEL_PTL_H_PCIE_RP1,
+ PCI_DID_INTEL_PTL_H_PCIE_RP2,
+ PCI_DID_INTEL_PTL_H_PCIE_RP3,
+ PCI_DID_INTEL_PTL_H_PCIE_RP4,
+ PCI_DID_INTEL_PTL_H_PCIE_RP5,
+ PCI_DID_INTEL_PTL_H_PCIE_RP6,
+ PCI_DID_INTEL_PTL_H_PCIE_RP7,
+ PCI_DID_INTEL_PTL_H_PCIE_RP8,
+ PCI_DID_INTEL_PTL_H_PCIE_RP9,
+ PCI_DID_INTEL_PTL_H_PCIE_RP10,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP1,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP2,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP3,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP4,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP5,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP6,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP7,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP8,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP9,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP10,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP11,
+ PCI_DID_INTEL_PTL_U_H_PCIE_RP12,
PCI_DID_INTEL_LNL_PCIE_RP1,
PCI_DID_INTEL_LNL_PCIE_RP2,
PCI_DID_INTEL_LNL_PCIE_RP3,
To view, visit change 83507. To unsubscribe, or for help writing mail filters, visit settings.