Arthur Heymans has uploaded this change for review.

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arch/x86/car.ld: Use REGION macro

The advantages of using the REGION macro:
- less boilerplate for defining start and end symbols
- overlap between regions checking
- automatic alignment

Change-Id: I9c327343eb40d3e2cc8513354ec3a83d803ff1ee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/arch/x86/car.ld
1 file changed, 4 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/36696/1
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 74fc74b..c601d2e 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -18,9 +18,7 @@
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
* aligned when using this option. */
- _pagetables = . ;
- . += 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES;
- _epagetables = . ;
+ REGION(pagetables, ., 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES, 4096)
#endif
/* Vboot work buffer only needs to be available when verified boot
* starts in bootblock. */
@@ -37,9 +35,7 @@
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
- _car_stack = .;
- . += CONFIG_DCACHE_BSP_STACK_SIZE;
- _ecar_stack = .;
+ REGION(car_stack, ., CONFIG_DCACHE_BSP_STACK_SIZE, 16)
#endif
/* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them above the car global section so that
@@ -47,22 +43,17 @@
* link address of these shared objects. */
PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
#if CONFIG(PAGING_IN_CACHE_AS_RAM)
- . = ALIGN(32);
/* Page directory pointer table resides here. There are 4 8-byte entries
* totalling 32 bytes that need to be 32-byte aligned. The reason the
* pdpt are not colocated with the rest of the page tables is to reduce
* fragmentation of the CAR space that persists across stages. */
- _pdpt = .;
- . += 32;
- _epdpt = .;
+ REGION(pdpt, ., 32, 32)
#endif

TIMESTAMP(., 0x200)

- _car_ehci_dbg_info = .;
/* Reserve sizeof(struct ehci_dbg_info). */
- . += 80;
- _ecar_ehci_dbg_info = .;
+ REGION(car_ehci_dbg_info, ., 80, ARCH_POINTER_ALIGN_SIZE)

/* _bss and _ebss provide symbols to per-stage
* variables that are not shared like the timestamp and the pre-ram
@@ -114,9 +105,6 @@
}

_bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-#if CONFIG(PAGING_IN_CACHE_AS_RAM)
-_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
-#endif
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#endif

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9c327343eb40d3e2cc8513354ec3a83d803ff1ee
Gerrit-Change-Number: 36696
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-MessageType: newchange