Tim Crawford has uploaded this change for review.
soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.
A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").
The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.
TGL also introduces parameters for customizing the default SVID:SSID.
These must be set or it will still use the FSP defaults.
Tested by checking lspci output on System76 darp7 (TGL-U).
References:
- b1fa231d76a ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S")
- TigerLake FSP Integration Guide
- Intel Document #631120-001
Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
M src/soc/intel/tigerlake/fsp_params.c
1 file changed, 55 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/56867/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 010ff02..0de6dfc 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -625,6 +625,61 @@
/* USB2 Phy Sus power gating setting override */
params->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable;
+ /*
+ * Prevent FSP from programming write-once subsystem IDs by providing
+ * a custom SSID table. Must have at least one entry for the FSP to
+ * use the table.
+ */
+ struct svid_ssid_init_entry {
+ union {
+ struct {
+ uint64_t reg:12; /* Register offset */
+ uint64_t function:3;
+ uint64_t device:5;
+ uint64_t bus:8;
+ uint64_t :4;
+ uint64_t segment:16;
+ uint64_t :16;
+ };
+ uint64_t segbusdevfuncregister;
+ };
+ struct {
+ uint16_t svid;
+ uint16_t ssid;
+ };
+ uint32_t reserved;
+ };
+
+ /*
+ * The xHCI and HDA devices have RW/L rather than RW/O registers for
+ * subsystem IDs and so must be written before FspSiliconInit locks
+ * them with their default values.
+ */
+ const pci_devfn_t devfn_table[] = { PCH_DEVFN_XHCI, PCH_DEVFN_HDA };
+ static struct svid_ssid_init_entry ssid_table[ARRAY_SIZE(devfn_table)];
+
+ for (i = 0; i < ARRAY_SIZE(devfn_table); i++) {
+ ssid_table[i].reg = PCI_SUBSYSTEM_VENDOR_ID;
+ ssid_table[i].device = PCI_SLOT(devfn_table[i]);
+ ssid_table[i].function = PCI_FUNC(devfn_table[i]);
+ dev = pcidev_path_on_root(devfn_table[i]);
+ if (dev) {
+ ssid_table[i].svid = dev->subsystem_vendor;
+ ssid_table[i].ssid = dev->subsystem_device;
+ }
+ }
+
+ params->SiSsidTablePtr = (uintptr_t)ssid_table;
+ params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table);
+
+ /*
+ * Replace the default SVID:SSID value with the values specified in
+ * the devicetree for the root device.
+ */
+ dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+ params->SiCustomizedSvid = dev->subsystem_vendor;
+ params->SiCustomizedSsid = dev->subsystem_device
+
mainboard_silicon_init_params(params);
}
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