Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons.
12 comments:
File src/mainboard/clevo/tgl-u/Kconfig:
Patch Set #6, Line 60: GPP_C14
GPP_C14_IRQ
File src/mainboard/clevo/tgl-u/Kconfig.name:
Patch Set #6, Line 7: MB/ME/MZ
nit: MZ at first, since it's the base for the other two?
File src/mainboard/clevo/tgl-u/variants/nv40mz/Makefile.inc:
bootblock-y += gpio.c
romstage-y += romstage.c
ramstage-y += gpio.c
ramstage-y += hda_verb.c
not needed. covered by tgl-u/Makefile.inc
File src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb:
Patch Set #6, Line 17: register "external_bypass" = "1"
could you check if PU5, PU8 are populated on the board?
Patch Set #6, Line 22: required
Is S0ix actually required?
S3 is deprecated on TGl
Patch Set #6, Line 83: register "CnviBtCore" = "true"
move down to cnvi dev
GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_C"
register "pmc_gpe0_dw1" = "PMC_GPP_E"
register "pmc_gpe0_dw2" = "PMC_GPD"
move down to pmc dev?
File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c:
add some comments?
//PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */
//PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */
configured in gpio_early
Patch Set #6, Line 210: PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT),
board uses espi vwire -> don't configure the gpio
File src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c:
* Disable AER for the SSD slot to support S0ix with SSDs running
* buggy firmware
any more details on this?
Patch Set #6, Line 12: params->CpuPcieRpAdvancedErrorReporting[0] = 0;
I'd also add this: […]
also params->CpuPcieRpLtrEnable[0] = 1;
To view, visit change 62498. To unsubscribe, or for help writing mail filters, visit settings.