Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, EricR Lai.

Subrata Banik uploaded patch set #3 to this change.

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soc/intel/alderlake: Implement report_cache_info() function

Make use of deterministic cache helper functions from Alder Lake
SoC code to print useful information during boot as below:

CPU: Genuine Intel(R) 0000
CPU: ID 906a0, Alderlake Platform, ucode: 00000019
CPU: AES supported, TXT supported, VT supported
Cache Information for Level3: assoc=12 par=1 line_size=64 sets=16384
@@ cache_size 0xc00000 bytes

Change-Id: I30a56266015d69abccb885b3f230689488ee0360
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/alderlake/bootblock/report_platform.c
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/55654/3

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I30a56266015d69abccb885b3f230689488ee0360
Gerrit-Change-Number: 55654
Gerrit-PatchSet: 3
Gerrit-Owner: Subrata Banik <subrata.banik@intel.com>
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