Elyes Haouas has uploaded this change for review.

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device/pciexp_device: Use 'PCI_BASE_ADDRESS_x' macros

Change-Id: I9b9700eec410776f66e0d6615ee8873e89f8c138
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
---
M src/device/pciexp_device.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/80447/1
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 969dbb00..e811592 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -708,7 +708,7 @@
struct resource *resource;

/* Add extra memory space */
- resource = new_resource(dev, 0x10);
+ resource = new_resource(dev, PCI_BASE_ADDRESS_0);
resource->size = CONFIG_PCIEXP_HOTPLUG_MEM;
resource->align = 12;
resource->gran = 12;
@@ -716,7 +716,7 @@
resource->flags |= IORESOURCE_MEM;

/* Add extra prefetchable memory space */
- resource = new_resource(dev, 0x14);
+ resource = new_resource(dev, PCI_BASE_ADDRESS_1);
resource->size = CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM;
resource->align = 12;
resource->gran = 12;
@@ -728,7 +728,7 @@
resource->flags |= IORESOURCE_ABOVE_4G;

/* Add extra I/O space */
- resource = new_resource(dev, 0x18);
+ resource = new_resource(dev, PCI_BASE_ADDRESS_2);
resource->size = CONFIG_PCIEXP_HOTPLUG_IO;
resource->align = 12;
resource->gran = 12;

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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9b9700eec410776f66e0d6615ee8873e89f8c138
Gerrit-Change-Number: 80447
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes Haouas <ehaouas@noos.fr>
Gerrit-MessageType: newchange