Angel Pons has uploaded this change for review.
sb/intel/bd82x6x: Make me_common.c a compilation unit
We need to make most things non-static so that the code builds.
Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/southbridge/intel/bd82x6x/Makefile.inc
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me.h
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/me_common.c
5 files changed, 47 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42019/1
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 9e34e96..cf9bf50 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -15,6 +15,7 @@
ramstage-y += usb_xhci.c
ramstage-y += me.c
ramstage-y += me_8.x.c
+ramstage-y += me_common.c
ramstage-y += smbus.c
ramstage-y += ../common/pciehp.c
@@ -24,7 +25,7 @@
ramstage-$(CONFIG_ELOG) += elog.c
-smm-y += smihandler.c me.c me_8.x.c pch.c
+smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c
romstage-y += early_smbus.c me_status.c
romstage-y += early_rcba.c
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 515f984..d2a3480 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -28,9 +28,6 @@
#include <vendorcode/google/chromeos/gnvs.h>
#endif
-/* FIXME: For verification purposes only */
-#include "me_common.c"
-
/* Get ME firmware version */
static int __unused mkhi_get_fw_version(void)
{
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 5aaf661..a55a1f2 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -221,6 +221,34 @@
ME_FIRMWARE_UPDATE_BIOS_PATH,
} me_bios_path;
+/* Defined in me_common.c for both ramstage and smm */
+const char *const me_get_bios_path_string(int path);
+
+void mei_read_dword_ptr(void *ptr, int offset);
+void mei_write_dword_ptr(void *ptr, int offset);
+
+#ifndef __SIMPLE_DEVICE__
+void pci_read_dword_ptr(struct device *dev, void *ptr, int offset);
+#endif
+
+void read_host_csr(struct mei_csr *csr);
+void write_host_csr(struct mei_csr *csr);
+
+void read_me_csr(struct mei_csr *csr);
+
+void write_cb(u32 dword);
+u32 read_cb(void);
+
+int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
+ void *req_data, void *rsp_data, int rsp_bytes);
+
+int mkhi_end_of_post(void);
+void update_mei_base_address(void);
+bool is_mei_base_address_valid(void);
+int intel_mei_setup(struct device *dev);
+int intel_me_extend_valid(struct device *dev);
+void intel_me_hide(struct device *dev);
+
/* Defined in me_status.c for both romstage and ramstage */
void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index fcf4dd3..1a331e9 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -28,9 +28,6 @@
#include <vendorcode/google/chromeos/gnvs.h>
#endif
-/* FIXME: For verification purposes only */
-#include "me_common.c"
-
static inline void print_cap(const char *name, int state)
{
printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c
index 790b870..83e7fe6 100644
--- a/src/southbridge/intel/bd82x6x/me_common.c
+++ b/src/southbridge/intel/bd82x6x/me_common.c
@@ -25,7 +25,7 @@
[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
};
-static inline const char *const me_get_bios_path_string(int path)
+const char *const me_get_bios_path_string(int path)
{
return me_bios_path_values[path];
}
@@ -70,14 +70,14 @@
* ME/MEI access helpers using memcpy to avoid aliasing.
*/
-static inline void mei_read_dword_ptr(void *ptr, int offset)
+void mei_read_dword_ptr(void *ptr, int offset)
{
u32 dword = read32(mei_base_address + (offset / sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
-static inline void mei_write_dword_ptr(void *ptr, int offset)
+void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
@@ -86,7 +86,7 @@
}
#ifndef __SIMPLE_DEVICE__
-static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
+void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
{
u32 dword = pci_read_config32(dev, offset);
memcpy(ptr, &dword, sizeof(dword));
@@ -94,28 +94,28 @@
}
#endif
-static inline void read_host_csr(struct mei_csr *csr)
+void read_host_csr(struct mei_csr *csr)
{
mei_read_dword_ptr(csr, MEI_H_CSR);
}
-static inline void write_host_csr(struct mei_csr *csr)
+void write_host_csr(struct mei_csr *csr)
{
mei_write_dword_ptr(csr, MEI_H_CSR);
}
-static inline void read_me_csr(struct mei_csr *csr)
+void read_me_csr(struct mei_csr *csr)
{
mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
}
-static inline void write_cb(u32 dword)
+void write_cb(u32 dword)
{
write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
-static inline u32 read_cb(void)
+u32 read_cb(void)
{
u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
@@ -310,8 +310,8 @@
return mei_wait_for_me_ready();
}
-static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
- void *req_data, void *rsp_data, int rsp_bytes)
+int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
+ void *req_data, void *rsp_data, int rsp_bytes)
{
if (mei_send_msg(mei, mkhi, req_data) < 0)
return -1;
@@ -321,7 +321,7 @@
}
/* Send END OF POST message to the ME */
-static int __unused mkhi_end_of_post(void)
+int mkhi_end_of_post(void)
{
struct mkhi_header mkhi = {
.group_id = MKHI_GROUP_ID_GEN,
@@ -351,12 +351,12 @@
#ifdef __SIMPLE_DEVICE__
-static inline void update_mei_base_address(void)
+void update_mei_base_address(void)
{
mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
}
-static inline bool is_mei_base_address_valid(void)
+bool is_mei_base_address_valid(void)
{
return mei_base_address && mei_base_address != (u32 *)0xfffffff0;
}
@@ -364,7 +364,7 @@
#else
/* Prepare ME for MEI messages */
-static int intel_mei_setup(struct device *dev)
+int intel_mei_setup(struct device *dev)
{
struct resource *res;
struct mei_csr host;
@@ -391,7 +391,7 @@
}
/* Read the Extend register hash of ME firmware */
-static int intel_me_extend_valid(struct device *dev)
+int intel_me_extend_valid(struct device *dev)
{
struct me_heres status;
u32 extend[8] = {0};
@@ -438,7 +438,7 @@
}
/* Hide the ME virtual PCI devices */
-static void intel_me_hide(struct device *dev)
+void intel_me_hide(struct device *dev)
{
dev->enabled = 0;
pch_enable(dev);
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