Martin Roth (martinroth@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15031
-gerrit
commit ba4de1c4d15dc06a2f65c2b1f1af6b67f3e390bb Author: Vadim Bendebury vbendeb@chromium.org Date: Sun May 22 16:09:54 2016 -0700
gru: kevin: configure board GPIOs
Set board GPIOs as required and add their description into the appropriate section of the coreboot table, to make them available to depthcharge.
BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to use keyboard on Gru, which indicates that the EC interrupt GPIO is properly configured. The rest of the pins will be verified later.
Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727 Signed-off-by: Martin Roth martinroth@chromium.org Original-Commit-Id: e02a05f Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69 Original-Signed-off-by: Vadim Bendebury vbendeb@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/346631 --- src/mainboard/google/gru/bootblock.c | 4 ++++ src/mainboard/google/gru/chromeos.c | 24 +++++++++++++++++++----- src/soc/rockchip/rk3399/Makefile.inc | 2 ++ 3 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 1166d8a..a048188 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -21,6 +21,8 @@ #include <soc/spi.h> #include <console/console.h>
+#include "board.h" + void bootblock_mainboard_early_init(void) { /* Let gpio2ab io domains works at 1.8V. @@ -62,4 +64,6 @@ void bootblock_mainboard_init(void) write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index da57d86..4265f8d 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -15,15 +15,22 @@ */
#include <boot/coreboot_tables.h> +#include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
+#include "board.h" + void fill_lb_gpios(struct lb_gpios *gpios) { -} + struct lb_gpio chromeos_gpios[] = { + {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, + {GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"}, + {GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + };
-int get_developer_mode_switch(void) -{ - return 0; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
int get_recovery_mode_switch(void) @@ -33,5 +40,12 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void) { - return 0; + return !gpio_get(GPIO_WP); +} + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_EC_IRQ); } diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 68f346c..75b2a54 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -47,6 +47,8 @@ romstage-y += ../common/pwm.c romstage-y += timer.c romstage-y += romstage.c romstage-y += tsadc.c +romstage-y += gpio.c +romstage-y += ../common/gpio.c
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