Angel Pons uploaded patch set #6 to this change.

View Change

cpu/intel/haswell/haswell.h: Align with Broadwell

Sort MSR definitions, move MCHBAR registers to northbridge and relocate
C-state latency macros into the header.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/haswell/haswell_init.c
M src/northbridge/intel/haswell/registers/mchbar.h
3 files changed, 52 insertions(+), 56 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46914/6

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29
Gerrit-Change-Number: 46914
Gerrit-PatchSet: 6
Gerrit-Owner: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: newpatchset