[coreboot-gerrit] [M] Change in coreboot[master]: mb/intel/adlrvp: Enable ISH and UFS for reworked ADL-P RVP

[Cliff Huang (Code Review)]

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71740 )

Change subject: mb/intel/adlrvp: Enable ISH and UFS for reworked ADL-P RVP
......................................................................

mb/intel/adlrvp: Enable ISH and UFS for reworked ADL-P RVP

UFS support is added to ADL-P RVP. Rework is required for UFS to work.
Secondary CPU and PCH SSD slots will be disabled after rework.
ISH is also enabled as part of UFS enablement.
ISH UART0 is enabled. The SW5C1 on MICA3 needs to be set properly to
route ISH UART signals instead of CR50.
To enable PCH SSD slot, comment out the following in the overrides.cb:
device ref pcie_rp9 off end
device ref pcie_rp11 off end
device ref ufs on end

BUG=b:252785850
TEST=Check that UFS device is detected from lspci command.

Signed-off-by: Cliff Huang 
Change-Id: I812786b9a25c31bc008f055af90467d4edf6158e
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/gpio.c
M src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
3 files changed, 49 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/71740/1

diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 7a5f1ec..1a10304 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -43,6 +43,7 @@
    select MAINBOARD_HAS_TPM2
    select SPI_TPM
    select TPM_GOOGLE_CR50
+	select DRIVERS_INTEL_ISH

config BOARD_INTEL_ADLRVP_P_MCHP
    select BOARD_INTEL_ADLRVP_COMMON
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 3c43a74..d9b11cc 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -11,16 +11,16 @@
    /* GPIO A0-A6, A9-A10 default function is NF1 for eSPI interface when
      eSPI is enabled */

-	/* SSD1_PWREN  CPU SSD1 */
-	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	/* ISH UART0 TXD */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
    /* SSD1_RESET  CPU SSD1 */
    PAD_CFG_GPO(GPP_F20, 1, PLTRST),
    /* BT_RF_KILL_N */
    PAD_CFG_GPO(GPP_A13, 1, PLTRST),
    /* WLAN RST# */
    PAD_CFG_GPO(GPP_H2, 1, PLTRST),
-	/* WIFI_WAKE_N */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT),
+	/* ISH UART0 RXD */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
    /* x4 PCIE slot1 PWREN */
    PAD_CFG_GPO(GPP_H17, 0, PLTRST),
    /* x4 PCIE slot 1 RESET */
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
index c78189f..7c16b2f 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
@@ -103,5 +103,26 @@
    			end
    		end
    	end
+		# NOTE: The following changes are for ADL-P LP5 RVP with rework for UFS2.1 or UFS3.1.
+		# RVP UFS support changed to default, whereas rework is required.
+        #   a. Rework to route clk_src 4 that connected to the 2nd CPU SSD slot for UFS.
+        #   b. Rework to change rp9 and rp10, which is used to be PCH SSD lanes, for UFS1.
+        #   c. Rework for UFS reset signal.
+        #   d. Additional rework is needed to change 3.3v to 2.5v and 1.8v to 1.2v for UFS3.1.
+        #   d. When UFS is enabled, rp9 and rp10 function as UFS link.
+		# For RVP without UFS rework, NVMe/SSD device can only be connected to the first CPU
+		# SSD slot with the device config below.
+		#
+		device ref pcie4_1 off end
+		device ref pcie_rp9 off end
+		device ref pcie_rp11 off end
+		device ref ish on
+			chip drivers/intel/ish
+				register "add_acpi_dma_property" = "true"
+				device generic 0 on
+				end
+            end
+        end
+		device ref ufs on end
    end
 end