Patch Set 1:

Patch Set 1:

Well. Sure that actually works?

The pmtimer is used in case seabios runs on qemu and initializes the (virtual) acpi pci device.
I doubt this also happens when running as coreboot payload.

The TSC needs calibration, and seabios uses the PIT for that I think. Except when running virtualized on KVM, in that case (new enough) seabios can use kvmclock to figure the TSC
frequency.

Well, I have tested disabling PIT and PM timer in coreboot on real hardware (clevo l140cu, if that matters) and qemu. Both worked absolutely fine.

However, since that setting here is just a default, I'd be OK with keeping it

wait... I've had another look at the code. Maybe I was wrong. @Nico thanks for the hint
Could it be that it "works" because the tsc is not decalibrated that much in my case by pure chance?

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifd75800678707a92110682347c7cfb93e25109a4
Gerrit-Change-Number: 46301
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