Patch Set #1, Line 807:
bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
> returning zero, with no references to 16bit VGA decode. […]
If upstream bridge supports CTL_VGA16, it does not matter when downstream (including cardbus) bridges do not support it? Aliased addresses are already not decoded from the primary side of that upstream bridge?
I think the cleanest approach is to add VGA IO resource once when we encounter a VGA class device. If platform and configuration is such that CTL_VGA would be set without CTL_VGA16 (on the most upstream PCI bridge), then add those 63 aliased resources.
I can test something with aopen/dxplplusu, nb/intel/e7505 lacks CTL_VGA16. No AGP graphics cards around anymore, so I have to hack something for testing though. And we may have to sort out the mess on AMD side too...
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