Patrick Georgi submitted this change.
soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device
There is no PCI host interface for this version of CNVi BT.
CNVi BT on Tigerlake is an USB device.
Change-Id: Ib71a827c36dfac55c3e5ce586b00a26fc6264464
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50900
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/intel/tigerlake/acpi/pci_irqs.asl
M src/soc/intel/tigerlake/chipset.cb
M src/soc/intel/tigerlake/include/soc/pci_devs.h
3 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
index 6f5f4bc..5bb30f0 100644
--- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
@@ -53,7 +53,6 @@
/* D16 */
Package(){0x0010FFFF, 0, 0, 23 },
Package(){0x0010FFFF, 1, 0, 22 },
- Package(){0x0010FFFF, 2, 0, 18 },
Package(){0x0010FFFF, 3, 0, 19 },
/* D13 */
Package(){0x000DFFFF, 0, 0, 16 },
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb
index d4bc76c..e81f0524 100644
--- a/src/soc/intel/tigerlake/chipset.cb
+++ b/src/soc/intel/tigerlake/chipset.cb
@@ -56,7 +56,6 @@
device pci 0d.2 alias tbt_dma0 off end
device pci 0d.3 alias tbt_dma1 off end
device pci 0e.0 alias vmd off end
- device pci 10.2 alias cnvi_bt off end
device pci 10.6 alias thc0 off end
device pci 10.7 alias thc1 off end
device pci 12.0 alias ish off end
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index b05ed13..af1453b 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -74,10 +74,8 @@
/* PCH Devices */
#define PCH_DEV_SLOT_SIO0 0x10
-#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2)
#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6)
#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7)
-#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2)
#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6)
#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7)
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