WANG Siyuan (wangsiyuanbuaa@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11747
-gerrit
commit 25410f81116fef49c5ce790dd624617d61666f6b Author: WANG Siyuan wangsiyuanbuaa@gmail.com Date: Tue Aug 18 06:28:02 2015 +0800
AMD Bettong DSDT table: Declare memory between TOM1 and 0xFED40000 for PCI MMIO
In current code, _SB.PCI0 declare MMIO between TOM1 and 4GB. This is not correct because higher MMIO space is reserved by _SB rather than _SB.PCI0. For example: [0xFEDC2000 - 0xFEDC5FFF] reserved for FCH I2C [0xFEDC6000 - 0xFEDC8FFF] reserved for FCH UART
Change-Id: I922d8c6a8ff1433582c70f86d5636171394af283 Signed-off-by: WANG Siyuan wangsiyuanbuaa@gmail.com Signed-off-by: WANG Siyuan SiYuan.Wang@amd.com --- src/southbridge/amd/pi/hudson/acpi/fch.asl | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index cee721f..6076cde 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -120,16 +120,12 @@ Method(_CRS, 0) { CreateDWordField(CRES, ^MMIO._LEN, MM1L)
/* - * Declare memory between TOM1 and 4GB as available + * Declare memory between TOM1 and 0xFED40000 as available * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). + * TODO: change the hardcoded value. */ Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) + Subtract(0xFED40000, TOM1, Local0) Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */