HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14976
-gerrit
commit 35c0b28f3d6f6349a29546c925a1015dfb97bc3a Author: Elyes HAOUAS ehaouas@noos.fr Date: Thu May 26 19:53:29 2016 +0200
Added CL7 support
according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf" Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) page 16 and page 60, CL7 support added
Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/include/spd.h | 1 + src/include/spd_ddr2.h | 1 + 2 files changed, 2 insertions(+)
diff --git a/src/include/spd.h b/src/include/spd.h index ea1b355..7aaf4dd 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -145,6 +145,7 @@ enum spd_memory_type { #define SPD_CAS_LATENCY_DDR2_4 (1 << 4) #define SPD_CAS_LATENCY_DDR2_5 (1 << 5) #define SPD_CAS_LATENCY_DDR2_6 (1 << 6) +#define SPD_CAS_LATENCY_DDR2_7 (1 << 7)
/* SPD_SUPPORTED_BURST_LENGTHS values. */ #define SPD_BURST_LENGTH_1 1 diff --git a/src/include/spd_ddr2.h b/src/include/spd_ddr2.h index 21aacf6..a31b4aa 100644 --- a/src/include/spd_ddr2.h +++ b/src/include/spd_ddr2.h @@ -80,6 +80,7 @@ #define SPD_CAS_LAT_4 (1<<4) #define SPD_CAS_LAT_5 (1<<5) #define SPD_CAS_LAT_6 (1<<6) + #define SPD_CAS_LAT_7 (1<<7)
#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */ #define SPD_TRRD 28