8 comments:
File Documentation/soc/amd/psp_integration.md:
Patch Set #2, Line 5: are beyond the scope, and may be found in AMD NDA publications.
beyond the scope ... of this document ...
Done. Was trying not to use the phrase "this document" again so soon.
Patch Set #2, Line 13: and shares the SPI flash storage that is used by BIOS.
where is the physical core of the PSP located? Presumably in the AP package right?
Right.
Patch Set #2, Line 19: * 0xfffa0000
what do each of these addresses point to?
Done
Patch Set #2, Line 102: | size | 0x02 | 32 | Size of PSP entry in bytes |
is this offset right? shouldn't it be 0x04?
Good catch, thank you. The original content was incorrect.
Patch Set #2, Line 147: * Refer to documentation for definitions.
which docs?
Done
Patch Set #2, Line 194: version. The version is located at offset 0x60 from the start of binary.
is it a 4 byte version scheme?
AFAICS
Patch Set #2, Line 265: | Reset Image | 0x02 | 1 | Boolean value to define the|
is this byte 2, bit 0, or bit 7?
Well the quick answer is it's byte 2, bit 0, 1, 2, etc. I could go either way on clarifying it vs. not. Since the architecture/endianness of the PSP is never mentioned, and it's an integration guide for an x86 product, I think it's normal to infer the correct order. I'm definitely not a good one to sample though.
Patch Set #2, Line 355: amdfw.rom, may then added directly into the coreboot image.
then be added
Done
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