Angel Pons has uploaded this change for review.
mb/asrock/h81m-hds: Factor out common MRC settings
There's no need to redefine common settings.
Change-Id: Ie4ced6efc8119afca070ce86634a3c31c6580d0f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/mainboard/asrock/h81m-hds/romstage.c
1 file changed, 42 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43110/1
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index 14a68ec..8d360e5 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -22,52 +22,48 @@
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data mainboard_pei_data = {
- .pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .hpet_address = HPET_ADDR,
- .rcba = (uintptr_t)DEFAULT_RCBA,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .temp_mmio_base = 0xfed08000,
- .system_type = 1, /* desktop/server */
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
- .ec_present = 0,
- .dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */
- .dimm_channel1_disabled = 2, /* Disable DIMM 1 on channel 1. */
- .max_ddr3_freq = 1600,
- .usb2_ports = {
- /* Length, Enable, OCn#, Location */
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
- { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
- },
- .usb3_ports = {
- /* Enable, OCn# */
- { 1, 0 },
- { 1, 0 },
- { 0, USB_OC_PIN_SKIP },
- { 0, USB_OC_PIN_SKIP },
- { 0, USB_OC_PIN_SKIP },
- { 0, USB_OC_PIN_SKIP },
- },
+ pei_data->system_type = 1; /* Desktop/Server */
+ pei_data->spd_addresses[0] = 0xa0;
+ pei_data->spd_addresses[2] = 0xa4;
+ pei_data->ec_present = 0;
+ /*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+ pei_data->dimm_channel0_disabled = 2;
+ pei_data->dimm_channel1_disabled = 2;
+ pei_data->max_ddr3_freq = 1600;
+
+ struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
+ { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
};
- *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
+ struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ { 1, 0 },
+ { 1, 0 },
+ { 0, USB_OC_PIN_SKIP },
+ { 0, USB_OC_PIN_SKIP },
+ { 0, USB_OC_PIN_SKIP },
+ { 0, USB_OC_PIN_SKIP },
+ };
+
+ memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
+ memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
}
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