Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2978
-gerrit
commit 2fcd2d1ba16f3daf28be2b6c685e2b91842debd6 Author: Aaron Durbin adurbin@chromium.org Date: Wed Mar 27 21:13:02 2013 -0500
lynxpoint: fix enable_pm1() function
The new enable_pm1() function was doing 2 things wrong:
1. It was doing a RMW of the pm1 register. This means we were keeping around the enables from the OS during S3 resume. This is bad in the face of the RTC alarm waking us up because it would cause an infinite stream of SMIs. 2. The register size of PM1_EN is 16-bits. However, the previous implementation was accessing it as a 32-bit register.
The PM1 enables should only be set to what we expect to handle in the firmware before the OS changes to ACPI mode.
Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/southbridge/intel/lynxpoint/pch.h | 2 +- src/southbridge/intel/lynxpoint/pmutil.c | 22 +++++++++++++++++----- 2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a48e0a4..7246739 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -139,7 +139,7 @@ void enable_pm1_control(u32 mask); void disable_pm1_control(u32 mask); /* PM1 */ u16 clear_pm1_status(void); -void enable_pm1(u32 mask); +void enable_pm1(u16 events); u32 clear_smi_status(void); /* SMI */ void enable_smi(u32 mask); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 3a0b70b..ea1dc65 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -29,6 +29,7 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> +#include <pc80/mc146818rtc.h> #include "pch.h"
#if CONFIG_INTEL_LYNXPOINT_LP @@ -104,6 +105,19 @@ static u16 reset_pm1_status(void) { u16 pm1_sts = inw(get_pmbase() + PM1_STS); outw(pm1_sts, get_pmbase() + PM1_STS); + +#if 0 + if (pm1_sts & RTC_STS) { + u8 cmos_status; + + cmos_status = cmos_read(RTC_REG_B); + printk(BIOS_DEBUG, "RTC REG B: %02X\n", cmos_status); + /* read RTC status register to disable the interrupt */ + cmos_status = cmos_read(RTC_REG_C); + printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status); + } +#endif + return pm1_sts; }
@@ -137,12 +151,10 @@ u16 clear_pm1_status(void) return print_pm1_status(reset_pm1_status()); }
-/* Enable PM1 event */ -void enable_pm1(u32 mask) +/* Set the PM1 register to events */ +void enable_pm1(u16 events) { - u32 pm1_en = inl(get_pmbase() + PM1_EN); - pm1_en |= mask; - outl(pm1_en, get_pmbase() + PM1_EN); + outw(events, get_pmbase() + PM1_EN); }