Werner Zeh submitted this change.
mb/intel/ehlcrb: Remove ChromeOS support from mainboard
Since ChromeOS is not officially supported for EHL CRB, removing
ChromeOS related codes. Here are the change details:
- Remove ChromeOS related kconfig switches, including
SOC_INTEL_CSE_LITE_SKU which has dependency on ChromeOS flag
- Remove chromeos.c file
- Remove ChromeOS dsdt related codes from dsdt.asl & mainboard.c
- Remove ChromeOS GPIO related codes from variants.h & gpio.c
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I4aabd40a4b46d4e64534b99e84e0523eaeaff816
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
M src/mainboard/intel/elkhartlake_crb/Kconfig
M src/mainboard/intel/elkhartlake_crb/Makefile.inc
D src/mainboard/intel/elkhartlake_crb/chromeos.c
M src/mainboard/intel/elkhartlake_crb/dsdt.asl
M src/mainboard/intel/elkhartlake_crb/mainboard.c
M src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
7 files changed, 0 insertions(+), 98 deletions(-)
diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig
index 14c2b93..07dc311 100644
--- a/src/mainboard/intel/elkhartlake_crb/Kconfig
+++ b/src/mainboard/intel/elkhartlake_crb/Kconfig
@@ -16,11 +16,9 @@
select HAVE_SPD_IN_CBFS
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
- select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_ELKHARTLAKE
select SOC_INTEL_COMMON_BLOCK_DTT
- select SOC_INTEL_CSE_LITE_SKU
config MAINBOARD_DIR
string
@@ -46,16 +44,6 @@
int
default 512
-config CHROMEOS
- bool
- default y
- select GBB_FLAG_FORCE_DEV_SWITCH_ON
- select GBB_FLAG_FORCE_DEV_BOOT_USB
- select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
- select GBB_FLAG_FORCE_MANUAL_RECOVERY
- select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
- select HAS_RECOVERY_MRC_CACHE
-
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2
diff --git a/src/mainboard/intel/elkhartlake_crb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/Makefile.inc
index 2ac1b07..cf9e1c9 100644
--- a/src/mainboard/intel/elkhartlake_crb/Makefile.inc
+++ b/src/mainboard/intel/elkhartlake_crb/Makefile.inc
@@ -3,15 +3,10 @@
subdirs-y += spd
bootblock-y += bootblock.c
-bootblock-$(CONFIG_CHROMEOS) += chromeos.c
-verstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += romstage_fsp_params.c
romstage-y += board_id.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
ramstage-y += board_id.c
diff --git a/src/mainboard/intel/elkhartlake_crb/chromeos.c b/src/mainboard/intel/elkhartlake_crb/chromeos.c
deleted file mode 100644
index c59fac8..0000000
--- a/src/mainboard/intel/elkhartlake_crb/chromeos.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <baseboard/gpio.h>
-#include <baseboard/variants.h>
-#include <boot/coreboot_tables.h>
-#include <gpio.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
- struct lb_gpio chromeos_gpios[] = {
- {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
- {-1, ACTIVE_HIGH, 0, "power"},
- {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
- };
- lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-
-#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
-int get_lid_switch(void)
-{
- /* Lid always open */
- return 1;
-}
-
-int get_recovery_mode_switch(void)
-{
- return 0;
-}
-
-#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
-
-int get_write_protect_state(void)
-{
- /* No write protect */
- return 0;
-}
-
-void mainboard_chromeos_acpi_generate(void)
-{
- const struct cros_gpio *gpios;
- size_t num;
-
- gpios = variant_cros_gpios(&num);
- chromeos_acpi_gpio_generate(gpios, num);
-}
diff --git a/src/mainboard/intel/elkhartlake_crb/dsdt.asl b/src/mainboard/intel/elkhartlake_crb/dsdt.asl
index 2faa511..dcbf380 100644
--- a/src/mainboard/intel/elkhartlake_crb/dsdt.asl
+++ b/src/mainboard/intel/elkhartlake_crb/dsdt.asl
@@ -29,21 +29,5 @@
}
}
-#if CONFIG(CHROMEOS)
- /* Chrome OS specific */
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-#endif
-
-#if CONFIG(EC_GOOGLE_CHROMEEC)
- /* Chrome OS Embedded Controller */
- Scope (\_SB.PCI0.LPCB)
- {
- /* ACPI code for EC SuperIO functions */
- #include <ec/google/chromeec/acpi/superio.asl>
- /* ACPI code for EC functions */
- #include <ec/google/chromeec/acpi/ec.asl>
- }
-#endif
-
#include <southbridge/intel/common/acpi/sleepstates.asl>
}
diff --git a/src/mainboard/intel/elkhartlake_crb/mainboard.c b/src/mainboard/intel/elkhartlake_crb/mainboard.c
index 315d47d..efba386 100644
--- a/src/mainboard/intel/elkhartlake_crb/mainboard.c
+++ b/src/mainboard/intel/elkhartlake_crb/mainboard.c
@@ -7,7 +7,6 @@
#include <soc/gpio.h>
#include <soc/pcr_ids.h>
#include <smbios.h>
-#include <vendorcode/google/chromeos/chromeos.h>
#define SERIAL_IO_PCR_GPPRVRW4 0x60C
@@ -23,11 +22,6 @@
pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8);
}
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
-}
-
const char *smbios_system_sku(void)
{
static const char *sku_str = "sku2147483647"; /* sku{0-1} */
@@ -36,5 +30,4 @@
struct chip_operations mainboard_ops = {
.init = mainboard_init,
- .enable_dev = mainboard_enable,
};
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h
index 8b6d0bd..53bb75a 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h
@@ -6,13 +6,11 @@
#include <soc/gpio.h>
#include <soc/meminit.h>
#include <stdint.h>
-#include <vendorcode/google/chromeos/chromeos.h>
/* The following 2 functions return the gpio table and fill in the number
* of entries for each table. */
const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);
-const struct cros_gpio *variant_cros_gpios(size_t *num);
/* This function returns SPD related FSP-M mainboard configs */
const struct mb_cfg *variant_memcfg_config(uint8_t board_id);
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
index f01202b..fe2aff7 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
@@ -25,13 +25,3 @@
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
-
-static const struct cros_gpio cros_gpios[] = {
- CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
-};
-
-const struct cros_gpio *variant_cros_gpios(size_t *num)
-{
- *num = ARRAY_SIZE(cros_gpios);
- return cros_gpios;
-}
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