Felix Singer has uploaded this change for review.
intel ehl mainboards: Move PcieRpEnable option below dt entries
There is work being done on better integrating the root port entries
from the devicetree by hooking up the FSP option PcieRpEnable to them,
which supersedes the devicetree option.
Change-Id: I3b14704916bb8105837257c271576f30cf62138b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
5 files changed, 51 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79961/1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 6994e8c..c34907f 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -40,11 +40,6 @@
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
@@ -157,11 +152,21 @@
device pci 1a.0 on end # eMMC
- device pci 1c.0 on end # RP1 (pcie0 single VC)
- device pci 1c.1 on end # RP2 (pcie0 single VC)
- device pci 1c.2 on end # RP3 (pcie0 single VC)
- device pci 1c.3 on end # RP4 (pcie0 single VC)
- device pci 1c.6 on end # RP7 (pcie3 multi VC)
+ device pci 1c.0 on # RP1 (pcie0 single VC)
+ register "PcieRpEnable[0]" = "1"
+ end
+ device pci 1c.1 on # RP2 (pcie0 single VC)
+ register "PcieRpEnable[1]" = "1"
+ end
+ device pci 1c.2 on # RP3 (pcie0 single VC)
+ register "PcieRpEnable[2]" = "1"
+ end
+ device pci 1c.3 on # RP4 (pcie0 single VC)
+ register "PcieRpEnable[3]" = "1"
+ end
+ device pci 1c.6 on # RP7 (pcie3 multi VC)
+ register "PcieRpEnable[6]" = "1"
+ end
device pci 1e.0 on end # UART0
device pci 1e.1 on end # UART1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index f14c225..a36ea16 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -40,8 +40,6 @@
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
@@ -176,8 +174,12 @@
device pci 1a.0 on end # eMMC
device pci 1a.1 on end # SD
- device pci 1c.1 on end # RP2 (pcie0 single VC)
- device pci 1c.6 on end # RP7 (pcie3 multi VC)
+ device pci 1c.1 on # RP2 (pcie0 single VC)
+ register "PcieRpEnable[1]" = "1"
+ end
+ device pci 1c.6 on # RP7 (pcie3 multi VC)
+ register "PcieRpEnable[6]" = "1"
+ end
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
index 9a0142c..d35bcdd 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
@@ -40,9 +40,6 @@
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
@@ -183,9 +180,15 @@
device pci 1a.0 on end # eMMC
device pci 1a.1 on end # SD
- device pci 1c.1 on end # RP2
- device pci 1c.2 on end # RP3
- device pci 1c.4 on end # RP5
+ device pci 1c.1 on # RP2
+ register "PcieRpEnable[1]" = "1"
+ end
+ device pci 1c.2 on # RP3
+ register "PcieRpEnable[2]" = "1"
+ end
+ device pci 1c.4 on # RP5
+ register "PcieRpEnable[4]" = "1"
+ end
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
index e99dd48..0f1650a4 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/devicetree.cb
@@ -40,11 +40,6 @@
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
@@ -178,11 +173,21 @@
device pci 1a.0 on end # eMMC
device pci 1a.1 on end # SD
- device pci 1c.0 on end # RP1 (pcie0 single VC)
- device pci 1c.1 on end # RP2 (pcie0 single VC)
- device pci 1c.2 on end # RP3 (pcie0 single VC)
- device pci 1c.3 on end # RP4 (pcie0 single VC)
- device pci 1c.4 on end # RP5 (pcie1 multi VC)
+ device pci 1c.0 on # RP1 (pcie0 single VC)
+ register "PcieRpEnable[0]" = "1"
+ end
+ device pci 1c.1 on # RP2 (pcie0 single VC)
+ register "PcieRpEnable[1]" = "1"
+ end
+ device pci 1c.2 on # RP3 (pcie0 single VC)
+ register "PcieRpEnable[2]" = "1"
+ end
+ device pci 1c.3 on # RP4 (pcie0 single VC)
+ register "PcieRpEnable[3]" = "1"
+ end
+ device pci 1c.4 on # RP5 (pcie1 multi VC)
+ register "PcieRpEnable[4]" = "1"
+ end
device pci 1e.0 on end # UART0
device pci 1e.1 on end # UART1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
index 53ea1f6..6c1cf8b 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb
@@ -40,8 +40,6 @@
register "SkipCpuReplacementCheck" = "1"
# PCIe root ports related UPDs
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[6]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
@@ -183,8 +181,12 @@
device pci 1a.0 on end # eMMC
device pci 1a.1 on end # SD
- device pci 1c.1 on end # RP2 (pcie0 single VC)
- device pci 1c.6 on end # RP7 (pcie3 multi VC)
+ device pci 1c.1 on # RP2 (pcie0 single VC)
+ register "PcieRpEnable[1]" = "1"
+ end
+ device pci 1c.6 on # RP7 (pcie3 multi VC)
+ register "PcieRpEnable[6]" = "1"
+ end
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0
To view, visit change 79961. To unsubscribe, or for help writing mail filters, visit settings.