Patrick Rudolph has uploaded this change for review.

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cpu/x86/64bit/entry64: Use ramstage code segment in ramstage

Change-Id: I232370dd92f11e7ce897d41514cced751c7e573d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/cpu/x86/64bit/entry64.inc
1 file changed, 8 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48176/1
diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc
index 65c0fdc..1376fcc 100644
--- a/src/cpu/x86/64bit/entry64.inc
+++ b/src/cpu/x86/64bit/entry64.inc
@@ -14,9 +14,15 @@
#if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0
#error pagetables must be 4KiB aligned!
#endif
+#if defined(__RAMSTAGE__)
+#include <arch/ram_segs.h>
+#define CODE_SEG64 RAM_CODE_SEG64
+#else
+#include <arch/rom_segs.h>
+#define CODE_SEG64 ROM_CODE_SEG64
+#endif

#include <cpu/x86/msr.h>
-#include <arch/rom_segs.h>

setup_longmode:
/* Get page table address */
@@ -42,7 +48,7 @@
movl %eax, %cr0

/* use long jump to switch to 64-bit code segment */
- ljmp $ROM_CODE_SEG64, $__longmode_start
+ ljmp $CODE_SEG64, $__longmode_start
.code64
__longmode_start:


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I232370dd92f11e7ce897d41514cced751c7e573d
Gerrit-Change-Number: 48176
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-MessageType: newchange