Subrata Banik submitted this change.
soc/intel/alderlake: Perform `heci_finalize` prior to booting to OS
`heci_finalize` ensures to put all heci devices to D3 by setting the
D0i3 bit prior to booting to the OS.
BUG=b:200644229
TEST=Verified D0i3 bit is set for all HECI devices prior to booting
to OS.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
M src/soc/intel/alderlake/finalize.c
1 file changed, 19 insertions(+), 0 deletions(-)
diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
index 6e2406a..c821e25 100644
--- a/src/soc/intel/alderlake/finalize.c
+++ b/src/soc/intel/alderlake/finalize.c
@@ -13,6 +13,7 @@
#include <cpu/x86/smm.h>
#include <device/mmio.h>
#include <device/pci.h>
+#include <intelblocks/cse.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
@@ -90,6 +91,23 @@
sa_lock_pam();
}
+static void heci_finalize(void)
+{
+ unsigned int cse_dev[] = {
+ PCH_DEVFN_CSE,
+ PCH_DEVFN_CSE_2,
+ PCH_DEVFN_CSE_3,
+ PCH_DEVFN_CSE_4
+ };
+
+ for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
+ if (!is_cse_devfn_visible(cse_dev[i]))
+ continue;
+
+ set_cse_device_state(cse_dev[i], DEV_IDLE);
+ }
+}
+
static void soc_finalize(void *unused)
{
printk(BIOS_DEBUG, "Finalizing chipset.\n");
@@ -98,6 +116,7 @@
apm_control(APM_CNT_FINALIZE);
tbt_finalize();
sa_finalize();
+ heci_finalize();
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);
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