Patrick Georgi submitted this change.
cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode
* Use heap for linker script calculated constant to fix relocation
symbols in mixed assembly code.
Tested on HPZ220:
* Still boots in x86_32.
Tested on Lenovo T410:
* Doesn't need the MMX register fix in long mode.
Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
A src/cpu/intel/car/cache_as_ram_symbols.inc
M src/cpu/intel/car/non-evict/cache_as_ram.S
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc
new file mode 100644
index 0000000..857e039
--- /dev/null
+++ b/src/cpu/intel/car/cache_as_ram_symbols.inc
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Trick the linker into supporting x86_64 relocations in 32bit code */
+#if ENV_X86_64
+#define uintptr_t quad
+#else
+#define uintptr_t long
+#endif
+
+rom_mtrr_mask:
+.uintptr_t _rom_mtrr_mask
+
+rom_mtrr_base:
+.uintptr_t _rom_mtrr_base
+
+car_mtrr_mask:
+.uintptr_t _car_mtrr_mask
+
+car_mtrr_start:
+.uintptr_t _car_mtrr_start
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index d087365..cde1ca3 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -9,6 +9,8 @@
.global bootblock_pre_c_entry
+#include <cpu/intel/car/cache_as_ram_symbols.inc>
+
.code32
_cache_as_ram_setup:
@@ -83,11 +85,10 @@
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
-
post_code(0x23)
/* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx
- movl $_car_mtrr_start, %eax
+ movl car_mtrr_start, %eax
orl $MTRR_TYPE_WRBACK, %eax
xorl %edx, %edx
wrmsr
@@ -96,20 +97,20 @@
/* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
- movl $_car_mtrr_mask, %eax
+ mov car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
- movl $_rom_mtrr_base, %eax
+ mov rom_mtrr_base, %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
- movl $_rom_mtrr_mask, %eax
+ mov rom_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr
@@ -207,8 +208,19 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
- subl $4, %esp
+#if ENV_X86_64
+
+ #include <cpu/x86/64bit/entry64.inc>
+
+ movd %mm2, %rdi
+ shlq $32, %rdi
+ movd %mm1, %rsi
+ or %rsi, %rdi
+ movd %mm0, %rsi
+
+#else
+ subl $4, %esp
/* push TSC and BIST to stack */
movd %mm0, %eax
pushl %eax /* BIST */
@@ -216,6 +228,7 @@
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */
+#endif
before_c_entry:
post_code(0x29)
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