2 comments:
Patch Set #4, Line 11: "Store (Or(ShiftLeft (Arg0, 4), 0xf), ^^DSPC.BRTC)" and "^^DSPC.BRTC = ((Arg0 << 0x04) | 0x0F)"
If it should be the same, report this to the IASL developers?
Reported.
Thx
File src/northbridge/intel/i945/acpi/igd.asl:
Due to the problem with the IASL optimization, split the commit into two, where one doesn’t change t […]
let wait acpica's developers answer
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